Patents by Inventor Mangesh P. Nijasure
Mangesh P. Nijasure has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10796483Abstract: Techniques for removing reset indices from, and identifying primitives in, an index stream that defines a set of primitives to be rendered, are disclosed. The index stream may be specified by an application program executing on the central processing unit. The technique involves classifying the primitive topology for the index stream as either requiring an offset-based technique or requiring a non-offset-based technique. This classification is done by determining whether, according to the primitive topology, each subsequent index can form a primitive with prior indices (e.g., line strip, triangle strip). If each subsequent index can form a primitive with prior indices, then the technique used is the non-offset-based technique. If each subsequent index does not form a primitive with prior indices, but instead at least two indices are required to form a new primitive (e.g., line list, triangle list), then the technique used is the offset-based technique.Type: GrantFiled: January 22, 2019Date of Patent: October 6, 2020Assignee: Advanced Micro Devices, Inc.Inventors: Saad Arrabi, Mangesh P. Nijasure, Todd Martin
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Publication number: 20200193703Abstract: A method of deferred vertex attribute shading includes computing, at a graphics processing pipeline of a graphics processing unit (GPU), a plurality of vertex attributes for vertices of each primitive of a set of primitives. The plurality of vertex attributes to be computed includes a vertex position attribute and at least a first non-position attribute for each primitive. One or more primitives of the set of primitives that do not contribute to a rendered image are discarded based upon the vertex position attribute for vertices of the set of primitives. A set of surviving primitives is generated based on the culling and deferred attribute shading is performed for at least a second non-position attribute for vertices of the set of surviving primitives.Type: ApplicationFiled: December 17, 2018Publication date: June 18, 2020Inventors: Brian J. FAVELA, Todd MARTIN, Mangesh P. NIJASURE
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Publication number: 20200035017Abstract: Improvements to graphics processing pipelines are disclosed. More specifically, the vertex shader stage, which performs vertex transformations, and the hull or geometry shader stages, are combined. If tessellation is disabled and geometry shading is enabled, then the graphics processing pipeline includes a combined vertex and graphics shader stage. If tessellation is enabled, then the graphics processing pipeline includes a combined vertex and hull shader stage. If tessellation and geometry shading are both disabled, then the graphics processing pipeline does not use a combined shader stage. The combined shader stages improve efficiency by reducing the number of executing instances of shader programs and associated resources reserved.Type: ApplicationFiled: October 2, 2019Publication date: January 30, 2020Applicant: Advanced Micro Devices, Inc.Inventors: Mangesh P. NIJASURE, Randy W. RAMSEY, Todd MARTIN
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Patent number: 10460513Abstract: Improvements to graphics processing pipelines are disclosed. More specifically, the vertex shader stage, which performs vertex transformations, and the hull or geometry shader stages, are combined. If tessellation is disabled and geometry shading is enabled, then the graphics processing pipeline includes a combined vertex and graphics shader stage. If tessellation is enabled, then the graphics processing pipeline includes a combined vertex and hull shader stage. If tessellation and geometry shading are both disabled, then the graphics processing pipeline does not use a combined shader stage. The combined shader stages improve efficiency by reducing the number of executing instances of shader programs and associated resources reserved.Type: GrantFiled: December 23, 2016Date of Patent: October 29, 2019Assignee: Advanced Micro Devices, Inc.Inventors: Mangesh P. Nijasure, Randy W. Ramsey, Todd Martin
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Patent number: 10453243Abstract: Processing of non-real-time and real-time workloads is performed using discrete pipelines. A first pipeline includes a first shader and one or more fixed function hardware blocks. A second pipeline includes a second shader that is configured to emulate the at least one fixed function hardware block. First and second memory elements store first state information for the first pipeline and second state information for the second pipeline, respectively. A non-real-time workload executing in the first pipeline is preempted at a primitive boundary in response to a real-time workload being dispatched for execution in the second pipeline. The first memory element retains the first state information in response to preemption of the non-real-time workload. The first pipeline is configured to resume processing the subsequent primitive on the basis of the first state information stored in the first memory element.Type: GrantFiled: January 3, 2019Date of Patent: October 22, 2019Assignee: Advanced Micro Devices, Inc.Inventors: Anirudh R. Acharya, Swapnil Sakharshete, Michael Mantor, Mangesh P. Nijasure, Todd Martin, Vineet Goel
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Publication number: 20190318527Abstract: Improvements in the graphics processing pipeline that allow multiple pipelines to cooperate to render a single frame are disclosed. Two approaches are provided. In a first approach, world-space pipelines for the different graphics processing pipelines process all work for draw calls received from a central processing unit (CPU). In a second approach, the world-space pipelines divide up the work. Work that is divided is synchronized and redistributed at various points in the world-space pipeline. In either approach, the triangles output by the world-space pipelines are distributed to the screen-space pipelines based on the portions of the render surface overlapped by the triangles. Triangles are rendered by screen-space pipelines associated with the render surface portions overlapped by those triangles.Type: ApplicationFiled: June 26, 2019Publication date: October 17, 2019Applicant: Advanced Micro Devices, Inc.Inventors: Mangesh P. NIJASURE, Todd MARTIN, Michael MANTOR
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Patent number: 10388056Abstract: Improvements in the graphics processing pipeline that allow multiple pipelines to cooperate to render a single frame are disclosed. Two approaches are provided. In a first approach, world-space pipelines for the different graphics processing pipelines process all work for draw calls received from a central processing unit (CPU). In a second approach, the world-space pipelines divide up the work. Work that is divided is synchronized and redistributed at various points in the world-space pipeline. In either approach, the triangles output by the world-space pipelines are distributed to the screen-space pipelines based on the portions of the render surface overlapped by the triangles. Triangles are rendered by screen-space pipelines associated with the render surface portions overlapped by those triangles.Type: GrantFiled: January 26, 2017Date of Patent: August 20, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Mangesh P. Nijasure, Todd Martin, Michael Mantor
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Publication number: 20190228574Abstract: Techniques for removing reset indices from, and identifying primitives in, an index stream that defines a set of primitives to be rendered, are disclosed. The index stream may be specified by an application program executing on the central processing unit. The technique involves classifying the primitive topology for the index stream as either requiring an offset-based technique or requiring a non-offset-based technique. This classification is done by determining whether, according to the primitive topology, each subsequent index can form a primitive with prior indices (e.g., line strip, triangle strip). If each subsequent index can form a primitive with prior indices, then the technique used is the non-offset-based technique. If each subsequent index does not form a primitive with prior indices, but instead at least two indices are required to form a new primitive (e.g., line list, triangle list), then the technique used is the offset-based technique.Type: ApplicationFiled: January 22, 2019Publication date: July 25, 2019Applicant: Advanced Micro Devices, Inc.Inventors: Saad Arrabi, Mangesh P. Nijasure, Todd Martin
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Publication number: 20190164328Abstract: Processing of non-real-time and real-time workloads is performed using discrete pipelines. A first pipeline includes a first shader and one or more fixed function hardware blocks. A second pipeline includes a second shader that is configured to emulate the at least one fixed function hardware block. First and second memory elements store first state information for the first pipeline and second state information for the second pipeline, respectively. A non-real-time workload executing in the first pipeline is preempted at a primitive boundary in response to a real-time workload being dispatched for execution in the second pipeline. The first memory element retains the first state information in response to preemption of the non-real-time workload. The first pipeline is configured to resume processing the subsequent primitive on the basis of the first state information stored in the first memory element.Type: ApplicationFiled: January 3, 2019Publication date: May 30, 2019Inventors: Anirudh R. ACHARYA, Swapnil SAKHARSHETE, Michael MANTOR, Mangesh P. NIJASURE, Todd MARTIN, Vineet GOEL
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Patent number: 10217280Abstract: Techniques for removing reset indices from, and identifying primitives in, an index stream that defines a set of primitives to be rendered, are disclosed. The index stream may be specified by an application program executing on the central processing unit. The technique involves classifying the primitive topology for the index stream as either requiring an offset-based technique or requiring a non-offset-based technique. This classification is done by determining whether, according to the primitive topology, each subsequent index can form a primitive with prior indices (e.g., line strip, triangle strip). If each subsequent index can form a primitive with prior indices, then the technique used is the non-offset-based technique. If each subsequent index does not form a primitive with prior indices, but instead at least two indices are required to form a new primitive (e.g., line list, triangle list), then the technique used is the offset-based technique.Type: GrantFiled: November 17, 2016Date of Patent: February 26, 2019Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Saad Arrabi, Mangesh P. Nijasure, Todd Martin
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Patent number: 10210650Abstract: Processing of non-real-time and real-time workloads is performed using discrete pipelines. A first pipeline includes a first shader and one or more fixed function hardware blocks. A second pipeline includes a second shader that is configured to emulate the at least one fixed function hardware block. First and second memory elements store first state information for the first pipeline and second state information for the second pipeline, respectively. A non-real-time workload executing in the first pipeline is preempted at a primitive boundary in response to a real-time workload being dispatched for execution in the second pipeline. The first memory element retains the first state information in response to preemption of the non-real-time workload. The first pipeline is configured to resume processing the subsequent primitive on the basis of the first state information stored in the first memory element.Type: GrantFiled: November 30, 2017Date of Patent: February 19, 2019Assignee: Advanced Micro Devices, Inc.Inventors: Anirudh R. Acharya, Swapnil Sakharshete, Michael Mantor, Mangesh P. Nijasure, Todd Martin, Vineet Goel
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Patent number: 10049487Abstract: Techniques for removing duplicate indices from an index stream are disclosed. The techniques involve dividing the indices into chunks. For any particular chunk, the techniques involve examining each index in the chunk to determine whether a “match” exists for that index within a reuse depth sliding window. The reuse depth sliding window includes a fixed number of indices immediately prior to the index being examined for a match. If a match exists, then the index is marked as non-unique and is assigned a position value equal to the position value of the matching index. If a match does not exist, then the index is marked as unique and assigned the next available position value for the chunk. After assigning position values to indices in a chunk, the indices in the chunk are transmitted to a vertex shader stage for processing in the order indicated by the position values.Type: GrantFiled: November 23, 2016Date of Patent: August 14, 2018Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Saad Arrabi, Mangesh P. Nijasure, Todd Martin
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Publication number: 20180211434Abstract: Techniques for generating a stereo image from a single set of input geometry in a three-dimensional rendering pipeline are disclosed. Vertices are processed through the end of the world-space pipeline. In the primitive assembler, at the end of the world-space pipeline, before perspective division, each clip-space vertex is duplicated. The primitive assembler generates this duplicated clip-space vertex using the y, z, and w coordinates of the original vertex and based on an x coordinate that is offset in the x-direction in clip-space as compared with the x coordinate of the original vertex. Both the original vertex clip-space vertex and the modified clip-space vertex are then sent through the rest of the pipeline for processing, including perspective division, viewport transform, rasterization, pixel shading, and other operations. The result is that a single set of input vertices is rendered into a stereo image.Type: ApplicationFiled: January 25, 2017Publication date: July 26, 2018Applicant: Advanced Micro Devices, Inc.Inventors: Mangesh P. Nijasure, Michael Mantor, Jeffrey M. Smith
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Publication number: 20180211435Abstract: Improvements in the graphics processing pipeline that allow multiple pipelines to cooperate to render a single frame are disclosed. Two approaches are provided. In a first approach, world-space pipelines for the different graphics processing pipelines process all work for draw calls received from a central processing unit (CPU). In a second approach, the world-space pipelines divide up the work. Work that is divided is synchronized and redistributed at various points in the world-space pipeline. In either approach, the triangles output by the world-space pipelines are distributed to the screen-space pipelines based on the portions of the render surface overlapped by the triangles. Triangles are rendered by screen-space pipelines associated with the render surface portions overlapped by those triangles.Type: ApplicationFiled: January 26, 2017Publication date: July 26, 2018Applicant: Advanced Micro Devices, Inc.Inventors: Mangesh P. Nijasure, Todd Martin, Michael Mantor
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Publication number: 20180144536Abstract: Techniques for removing duplicate indices from an index stream are disclosed. The techniques involve dividing the indices into chunks. For any particular chunk, the techniques involve examining each index in the chunk to determine whether a “match” exists for that index within a reuse depth sliding window. The reuse depth sliding window includes a fixed number of indices immediately prior to the index being examined for a match. If a match exists, then the index is marked as non-unique and is assigned a position value equal to the position value of the matching index. If a match does not exist, then the index is marked as unique and assigned the next available position value for the chunk. After assigning position values to indices in a chunk, the indices in the chunk are transmitted to a vertex shader stage for processing in the order indicated by the position values.Type: ApplicationFiled: November 23, 2016Publication date: May 24, 2018Applicant: Advanced Micro Devices, Inc.Inventors: Saad Arrabi, Mangesh P. Nijasure, Todd Martin
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Publication number: 20180137676Abstract: Techniques for removing reset indices from, and identifying primitives in, an index stream that defines a set of primitives to be rendered, are disclosed. The index stream may be specified by an application program executing on the central processing unit. The technique involves classifying the primitive topology for the index stream as either requiring an offset-based technique or requiring a non-offset-based technique. This classification is done by determining whether, according to the primitive topology, each subsequent index can form a primitive with prior indices (e.g., line strip, triangle strip). If each subsequent index can form a primitive with prior indices, then the technique used is the non-offset-based technique. If each subsequent index does not form a primitive with prior indices, but instead at least two indices are required to form a new primitive (e.g., line list, triangle list), then the technique used is the offset-based technique.Type: ApplicationFiled: November 17, 2016Publication date: May 17, 2018Applicant: Advanced Micro Devices, Inc.Inventors: Saad Arrabi, Mangesh P. Nijasure, Todd Martin
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Publication number: 20180082470Abstract: Improvements to graphics processing pipelines are disclosed. More specifically, the vertex shader stage, which performs vertex transformations, and the hull or geometry shader stages, are combined. If tessellation is disabled and geometry shading is enabled, then the graphics processing pipeline includes a combined vertex and graphics shader stage. If tessellation is enabled, then the graphics processing pipeline includes a combined vertex and hull shader stage. If tessellation and geometry shading are both disabled, then the graphics processing pipeline does not use a combined shader stage. The combined shader stages improve efficiency by reducing the number of executing instances of shader programs and associated resources reserved.Type: ApplicationFiled: December 23, 2016Publication date: March 22, 2018Applicant: Advanced Micro Devices, Inc.Inventors: Mangesh P. Nijasure, Randy W. Ramsey, Todd Martin
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Publication number: 20180082399Abstract: Improvements in the graphics processing pipeline are disclosed. More specifically, a new primitive shader stage performs tasks of the vertex shader stage or a domain shader stage if tessellation is enabled, a geometry shader if enabled, and a fixed function primitive assembler. The primitive shader stage is compiled by a driver from user-provided vertex or domain shader code, geometry shader code, and from code that performs functions of the primitive assembler. Moving tasks of the fixed function primitive assembler to a primitive shader that executes in programmable hardware provides many benefits, such as removal of a fixed function crossbar, removal of dedicated parameter and position buffers that are unusable in general compute mode, and other benefits.Type: ApplicationFiled: January 25, 2017Publication date: March 22, 2018Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Todd Martin, Mangesh P. Nijasure, Randy W. Ramsey, Michael Mantor, Laurent Lefebvre