Patents by Inventor Manh Anh Do

Manh Anh Do has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8242872
    Abstract: Embodiments of the invention provide a transformer comprising: a first coil element having a transverse axis along a transverse direction, the first coil element having p turns where p is greater than or equal to 1; and a second coil element having a transverse axis generally parallel to the transverse axis of the first coil element, the second coil element having n turns, where n is greater than or equal to 5p; wherein the first and second coil elements are arranged to provide electromagnetic coupling between the coil elements along a portion of a length of the second coil element in both a transverse direction parallel to the transverse axes and a lateral direction, wherein the lateral direction is a direction normal to the transverse axes.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: August 14, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Chee Chong Lim, Kok Wai Chew, Kiat Seng Yeo, Suh Fei Lim, Manh Anh Do, Lap Chan
  • Patent number: 8237531
    Abstract: An inductor circuit with high quality (Q) factor includes a primary inductor and a compensation sub-circuit. The compensation sub-circuit is electrically isolated from the primary inductor. The compensation sub-circuit is magnetically coupled with the primary inductor to compensate the loss in the primary inductor.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: August 7, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Ping Qiu, Chirn Chye Boon, Johnny Kok Wai Chew, Kiat Seng Yeo, Manh Anh Do, Lap Chan, Suh Fei Lim
  • Patent number: 7570144
    Abstract: An integrated transformer structure includes a first coil element associated with a transverse axis, the first coil element having at least one turn. The first coil element includes a first portion provided on a first lateral level, and a second portion provided on a second lateral level. The first and second lateral levels being mutually spaced apart along said transverse axis. The first and second portions being displaced laterally from said axis by different respective distances. At least one crossover portion of the first coil element, in which the first coil element being configured to provide a conducting path through at least a portion of the first portion of the first coil element to the crossover portion, through the crossover portion and subsequently through at least a portion of the second portion of the first coil element, in which any change of flow direction along said path is less than 90° in a lateral direction.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: August 4, 2009
    Assignees: Chartered Semiconductor Manufacturing, Ltd., Nanyang Technological University
    Inventors: Chee Chong Lim, Kok Wai Chew, Kiat Seng Yeo, Suh Fei Lim, Manh Anh Do, Lap Chan
  • Publication number: 20090167466
    Abstract: An inductor circuit with high quality (Q) factor includes a primary inductor and a compensation sub-circuit. The compensation sub-circuit is electrically isolated from the primary inductor. The compensation sub-circuit is magnetically coupled with the primary inductor to compensate the loss in the primary inductor.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD., NANYANG TECHNOLOGICAL UNIVERSITY
    Inventors: Ping QIU, Chirn Chye BOON, Johnny Kok Wai CHEW, Kiat Seng YEO, Manh Anh DO, Lap CHAN, Suh Fei LIM
  • Publication number: 20080284552
    Abstract: An integrated transformer structure includes a first coil element associated with a transverse axis, the first coil element having at least one turn. The first coil element includes a first portion provided on a first lateral level, and a second portion provided on a second lateral level. The first and second lateral levels being mutually spaced apart along said transverse axis. The first and second portions being displaced laterally from said axis by different respective distances. At least one crossover portion of the first coil element, in which the first coil element being configured to provide a conducting path through at least a portion of the first portion of the first coil element to the crossover portion, through the crossover portion and subsequently through at least a portion of the second portion of the first coil element, in which any change of flow direction along said path is less than 90° in a lateral direction.
    Type: Application
    Filed: May 18, 2007
    Publication date: November 20, 2008
    Applicants: Chartered Semiconductor Manufacturing, Ltd., Nanyang Technological University
    Inventors: Chee Chong Lim, Kok Wai Chew, Kiat Seng Yeo, Suh Fei Lim, Manh Anh Do, Lap Chan
  • Publication number: 20080284553
    Abstract: Embodiments of the invention provide a transformer comprising: a first coil element having a transverse axis along a transverse direction, the first coil element having p turns where p is greater than or equal to 1; and a second coil element having a transverse axis generally parallel to the transverse axis of the first coil element, the second coil element having n turns, where n is greater than or equal to 5 p; wherein the first and second coil elements are arranged to provide electromagnetic coupling between the coil elements along a portion of a length of the second coil element in both a transverse direction parallel to the transverse axes and a lateral direction, wherein the lateral direction is a direction normal to the transverse axes.
    Type: Application
    Filed: July 19, 2007
    Publication date: November 20, 2008
    Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD., NANYANG TECHNOLOGICAL UNIVERSITY
    Inventors: Chee Chong LIM, Kok Wai CHEW, Kiat Seng YEO, Suh Fei LIM, Manh Anh DO, Lap CHAN
  • Patent number: 7023315
    Abstract: A method of fabricating an inductor using bonding techniques in the manufacture of integrated circuits is described. Bonding pads are provided over a semiconductor substrate. Input/output connections are made to at least two of the bonding pads. A plurality of wire bond loops are made between each two of the bonding pads wherein the plurality of wire bond loops forms the inductor.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: April 4, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kiat Seng Yeo, Hai Peng Tan, Jianguo Ma, Manh Anh Do, Kok Wai Johnny Chew
  • Patent number: 6998953
    Abstract: A method of fabricating an inductor using bonding techniques in the manufacture of integrated circuits is described. Bonding pads are provided over a semiconductor substrate. Input/output connections are made to at least two of the bonding pads. A plurality of wire bond loops are made between each two of the bonding pads wherein the plurality of wire bond loops forms the inductor.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: February 14, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kiat Seng Yeo, Hai Peng Ian, Jiangud Ma, Manh Anh Do, Johnny Kok Wai Chew
  • Patent number: 6803848
    Abstract: A new structure and method is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of a helix coil design having upper level and lower level conductors further having an axis whereby the axis of the helix coil of the inductor is parallel to the plane of the underlying substrate. Under the first embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is uniform. Under the second embodiment of the invention the height of the helix coil of the inductor of the invention is uniform while a ferromagnetic core is inserted between the upper and the lower level conductors of the helix coil. Under the third embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is non-uniform.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: October 12, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kiat Seng Yeo, Hai Peng Tan, Jian Guo Ma, Manh Anh Do, Kok Wai Johnny Chew
  • Patent number: 6800533
    Abstract: A new structure is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of spiral design and perpendicular to the plane of the underlying substrate. Conductor line width can be selected as narrow or wide, ferromagnetic material can be used to fill the spaces between the conductors of the spiral inductor. The spiral inductor of the invention can further by used in series or in series with conventional horizontal inductors.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: October 5, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kiat Seng Yeo, Hai Peng Tan, Jian Guo Ma, Manh Anh Do, Kok Wai Johnny Chew
  • Publication number: 20030205778
    Abstract: A method of fabricating an inductor using bonding techniques in the manufacture of integrated circuits is described. Bonding pads are provided over a semiconductor substrate. Input/output connections are made to at least two of the bonding pads. A plurality of wire bond loops are made between each two of the bonding pads wherein the plurality of wire bond loops forms the inductor.
    Type: Application
    Filed: May 29, 2003
    Publication date: November 6, 2003
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Kiat Seng Yeo, Hat Peng Tan, Jianguo Ma, Manh Anh Do, Kok Wai Johnny Chew
  • Patent number: 6611188
    Abstract: A new structure is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of spiral design and perpendicular to the plane of the underlying substrate. Conductor line width can be selected as narrow or wide, ferromagnetic material can be used to fill the spaces between the conductors of the spiral inductor. The spiral inductor of the invention can further by used in series or in series with conventional horizontal inductors.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: August 26, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kiat Seng Yeo, Hai Yeng Tan, Jiang Guo Ma, Manh Anh Do, Kok Wai Johnny Chew
  • Patent number: 6586309
    Abstract: A method of fabricating an inductor using bonding techniques in the manufacture of integrated circuits is described. Bonding pads are provided over a semiconductor substrate. Input/output connections are made to at least two of the bonding pads. A plurality of wire bond loops are made between each two of the bonding pads wherein the plurality of wire bond loops forms the inductor.
    Type: Grant
    Filed: April 24, 2000
    Date of Patent: July 1, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kiat Seng Yeo, Hai Peng Tan, Jianguo Ma, Manh Anh Do, Kok Wai Johnny Chew
  • Patent number: 6535098
    Abstract: A new structure and method is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of a helix coil design having upper level and lower level conductors further having an axis whereby the axis of the helix coil of the inductor is parallel to the plane of the underlying substrate. Under the first embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is uniform. Under the second embodiment of the invention the height of the helix coil of the inductor of the invention is uniform while a ferromagnetic core is inserted between the upper and the lower level conductors of the helix coil. Under the third embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is non-uniform.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: March 18, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kiat Seng Yeo, Hai Peng Tan, Jian Guo Ma, Manh Anh Do, Kok Wai Johnny Chew
  • Publication number: 20030043010
    Abstract: A new structure and method is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of a helix coil design having upper level and lower level conductors further having an axis whereby the axis of the helix coil of the inductor is parallel to the plane of the underlying substrate. Under the first embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is uniform. Under the second embodiment of the invention the height of the helix coil of the inductor of the invention is uniform while a ferromagnetic core is inserted between the upper and the lower level conductors of the helix coil. Under the third embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is non-uniform.
    Type: Application
    Filed: October 15, 2002
    Publication date: March 6, 2003
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Kiat Seng Yeo, Hai Peng Tan, Jian Guo Ma, Manh Anh Do, Kok Wai Johnny Chew
  • Patent number: 6521939
    Abstract: A new MOS varactor device is described. A bottom electrode comprises a plurality of diffusion junctions in a semiconductor substrate. The semiconductor substrate may be n-type or p-type. The diffusion junctions are arranged in a two-dimensional array. The diffusion junction may be either n-type or p-type. The diffusion junctions may be contained in a p-well or an n-well. A dielectric layer overlies the semiconductor substrate. A top electrode overlies the dielectric layer. The top electrode comprises a single polygon containing a two-dimensional array of openings therein that exposes the diffusion junctions. The top electrode preferably comprises polysilicon. An interlevel dielectric layer overlies the top electrode and the diffusion junction. The interlevel dielectric layer has a two-dimensional array of contact openings that expose the underlying diffusion junctions. A patterned metal layer overlies the interlevel dielectric layer and contacts the diffusion junctions through the contact openings.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: February 18, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kiat-Seng Yeo, Chun Qi Geng, Kok-Wai Chew, Manh-Anh Do, Jian Guo Ma
  • Publication number: 20030013264
    Abstract: A new structure is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of spiral design and perpendicular to the plane of the underlying substrate. Conductor line width can be selected as narrow or wide, ferromagnetic material can be used to fill the spaces between the conductors of the spiral inductor. The spiral inductor of the invention can further by used in series or in series with conventional horizontal inductors.
    Type: Application
    Filed: September 3, 2002
    Publication date: January 16, 2003
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Kiat Seng Yeo, Hai Peng Tan, Jian Guo Ma, Manh Anh Do, Kok Wai Johnny Chew
  • Patent number: 6292060
    Abstract: In this invention a single additional capacitor is added to a tuned cascode LNA which boosts the circuit Q and the gain of the amplifier. The added capacitor creates a negative real part of the impedance which when combined with the impedance of the LC tank circuit improves both the Q and the gain of the amplifier. The capacitor does not dissipate any power, and being a passive device the capacitor does not add additional noise to the circuit. With an improved gain there is a much improved signal to noise ratio. The higher Q allows the amplifier to provide some additional bandpass and reduce image reduction requirements in subsequent amplifier stages.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: September 18, 2001
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kiat-Seng Yeo, Kok Lim Chan, Manh Anh Do, Jian Guo Ma, Johnny Kok Wai Chew