Patents by Inventor Mani Ayyar
Mani Ayyar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9798556Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.Type: GrantFiled: December 28, 2015Date of Patent: October 24, 2017Assignee: INTEL CORPORATIONInventors: Mani Ayyar, Eric Richard Delano, Ioannis Y. Schoinas, Akhilesh Kumar, Doddaballapur Jayasimha, Jose A. Vargas
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Publication number: 20160196153Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.Type: ApplicationFiled: December 28, 2015Publication date: July 7, 2016Applicant: INTEL CORPORATIONInventors: MANI AYYAR, ERIC RICHARD DELANO, IOANNIS Y. SCHOINAS, AKHILESH KUMAR, DODDABALLAPUR JAYASIMHA, JOSE A. VARGAS
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Patent number: 9223738Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.Type: GrantFiled: November 2, 2012Date of Patent: December 29, 2015Assignee: Intel CorporationInventors: Mani Ayyar, Eric Richard Delano, Ioannis Y. Schoinas, Akhilesh Kumar, Doddaballapur Jayasimha, Jose A. Vargas
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Patent number: 8606934Abstract: Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.Type: GrantFiled: January 5, 2009Date of Patent: December 10, 2013Assignee: Intel CorporationInventors: Mani Ayyar, Srinivas Chennupaty, Akhilesh Kumar, Doddabaliapur Narasimha-Murthy Jayasimha, Murugasamy Nachimuthu, Phanindra K. Mannava, Ioannis T. Schoinas
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Publication number: 20130304957Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.Type: ApplicationFiled: November 2, 2012Publication date: November 14, 2013Inventors: Mani Ayyar, Eric Richard Delano, Ioanns Y. Schoinas, Akhilesh Kumar, Doddaballapur Jayasimha, Jose A. Vargas
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Patent number: 8327113Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.Type: GrantFiled: September 23, 2008Date of Patent: December 4, 2012Assignee: Intel CorporationInventors: Mani Ayyar, Eric Delano, Ioannis T. Schoinas, Akhilesh Kumar, Jay Jayasimha, Jose A. Vargas
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Patent number: 8171121Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.Type: GrantFiled: September 23, 2008Date of Patent: May 1, 2012Assignee: Intel CorporationInventors: Mani Ayyar, Eric Delano, Ioannis T. Schoinas, Akhilesh Kumar, Jay Jayasimha, Jose A. Vargas
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Patent number: 7904751Abstract: Systems and methods for error handling are disclosed. The systems and methods may be utilized for single or multiple processor computer systems to handle errors in a coordinated manner between hardware and any firmware or software layers. A computer system includes a non volatile memory and at least one processor. A firmware error handling routine is stored on the non volatile memory. The firmware error handling routine is for handling errors. Each of the at least one processors detects errors. Each processor executes the firmware error handling routine on detecting an error. The executed firmware error handling routine handles the error. The executed firmware error handling routine also logs error information to a log. The systems and methods provide for coordinated error handling that enhance error recovery, provide error containment and maintain system availability.Type: GrantFiled: July 28, 2003Date of Patent: March 8, 2011Assignee: Intel CorporationInventors: Suresh Marisetty, Mani Ayyar, Nhon T. Quach, Bernard J. Lint
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Patent number: 7738484Abstract: Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.Type: GrantFiled: December 13, 2004Date of Patent: June 15, 2010Assignee: Intel CorporationInventors: Mani Ayyar, Srinivas Chennupaty, Akhilesh Kumar, Doddaballapur N. Jayasimha, Murugasamy Nachimuthu, Phanindra K. Mannava
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Patent number: 7734741Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.Type: GrantFiled: December 13, 2004Date of Patent: June 8, 2010Assignee: Intel CorporationInventors: Mani Ayyar, Eric Delano, Ioannis T. Schoinas, Akhilesh Kumar, Jay Jayasimha, Jose A. Vargas
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Publication number: 20090265472Abstract: Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.Type: ApplicationFiled: January 5, 2009Publication date: October 22, 2009Inventors: Mani Ayyar, Srinivas Chennupaty, Akhilesh Kumar, Doddabaliapur Narasimha-Murthy Jayasimha, Murugasamy Nachimuthu, Phanindra K. Mannava, Ioannis T. Schoinas
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Patent number: 7502959Abstract: A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.Type: GrantFiled: July 28, 2003Date of Patent: March 10, 2009Assignee: Intel CorporationInventors: Suresh Marisetty, George Thangadurai, Mani Ayyar
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Publication number: 20090055600Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.Type: ApplicationFiled: September 23, 2008Publication date: February 26, 2009Inventors: Mani Ayyar, Eric Delano, Ioannis T. Schoinas, Akhiles Kumar, Jay Jayasimha, Jose A. Vargas
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Publication number: 20090024715Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.Type: ApplicationFiled: September 23, 2008Publication date: January 22, 2009Inventors: Mani Ayyar, Eric Delano, Ioannis T. Schoinas, Akhiles Kumar, Jay Jayasimha, Jose A. Vargas
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Publication number: 20090019267Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.Type: ApplicationFiled: September 23, 2008Publication date: January 15, 2009Inventors: Mani Ayyar, Eric Delano, Ioannis T. Schoinas, Akhiles Kumar, Jay Jayashimha, Jose A. Vargas
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Patent number: 7433985Abstract: An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode (SMM). A conditional SMI inter-processor interrupt (IPI) message is broadcast to at least a processor. The SMI is processed without waiting for the at least processor to check into the SMM. A clear pending SMI is broadcast to the processors at end of SMI processing to clear a pending SMI condition.Type: GrantFiled: December 28, 2005Date of Patent: October 7, 2008Assignee: Intel CorporationInventors: Mani Ayyar, Ioannis Schoinas, Rama R. Menon, Aniruddha Vaidya, Akhilesh Kumar
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Publication number: 20070150632Abstract: An embodiment of the present invention is a technique to process system management interrupt. A system management interrupt (SMI) is received. The SMI is associated with a system management mode (SMM). A conditional SMI inter-processor interrupt (IPI) message is broadcast to at least a processor. The SMI is processed without waiting for the at least processor to check into the SMM. A clear pending SMI is broadcast to the processors at end of SMI processing to clear a pending SMI condition.Type: ApplicationFiled: December 28, 2005Publication date: June 28, 2007Inventors: Mani Ayyar, Ioannis Schoinas, Rama Menon, Aniruddha Vaidya, Akhilesh Kumar
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Patent number: 7117396Abstract: A firmware-based mechanism for creating, storing and retrieving variable-length records associated with error events occurring in a computer platform. The mechanism responds to error notifications by invoking a firmware-based error-handling module. The error-handling module retrieves processor-specific error information and may also interrogate the other components of the computer platform to determine their error status. Then, according to the nature of the discovered errors, the error-handling module may assemble the retrieved error information and status information into a variable-length error record, which the error-handling module may then store in a memory. On request from a processing agent, the error-handling module may retrieve a previously-stored error record and present it to the requesting agent. Thus, the invention provides a unified and standardized approach to computer error handling at the firmware level.Type: GrantFiled: December 28, 2001Date of Patent: October 3, 2006Assignee: Intel CorporationInventors: Eshwari P. Komarla, Suresh Marisetty, Mani Ayyar, Andrew J. Fish, Mohan J. Kumar, Shivnandan D. Kaushik
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Publication number: 20060184480Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.Type: ApplicationFiled: December 13, 2004Publication date: August 17, 2006Inventors: Mani Ayyar, Eric Delano, Ioannis Schoinas, Akhilesh Kumar, Jay Jayasimha, Jose Vargas
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Publication number: 20060126656Abstract: Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.Type: ApplicationFiled: December 13, 2004Publication date: June 15, 2006Inventors: Mani Ayyar, Srinivas Chennupaty, Akhilesh Kumar, Doddaballapur Jayasimha, Murugasamy Nachimuthu, Phanindra Mannava