Abstract: Methods, systems, and devices for receiver decision feedback equalization calibration are described. A memory system may support implementing respective decision feedback equalization (DFE) values at respective receivers using interpolation logic. For example, a calibration circuit may generate and store a quantity of candidate voltage values corresponding to the application of different DFE values at the receivers. The memory system may use the interpolation logic to generate (e.g., interpolate, generate) respective voltage values corresponding to a DFE value for application at a respective receiver based on the stored candidate voltage values. The interpolation logic may output the voltage values via a serial bus to each receiver, and each receiver may apply, to respectively received data, a DFE value corresponding to a respectively received voltage value.

Abstract: Methods, systems, and devices for data alignment for memory are described. A memory device may implement individual time adjustments to align portions of a multilevel signal modulated by a modulation scheme with three levels. In some cases, signal paths for generating and transmitting the portions of the multilevel signal may reference a clock signal, and adjustable delay circuits may apply individual delays to the clock signal received at each signal path. For example, a first adjustable delay circuit may apply a first time adjustment to the clock signal received at a first signal path for generating a first portion. And, a second adjustable delay circuit may apply a second time adjustment to the clock signal received at a second signal path for generating a second portion. Applying the time adjustments to the signal paths may align the portions of the multilevel signal in time, compared to the clock signal.

Abstract: Methods, systems, and devices for signal sampling with offset calibration are described. For example, sampling circuitry may include an input pair of transistors where input signals may be provided to gate nodes of the transistors, and an output signal may be generated based on a comparison of voltages of drain nodes of the transistors. In some examples, source nodes of the transistors may be coupled with each other, such as via a resistance, and each source node may be configured to be coupled with a ground node. In some examples, a conductive path between the source nodes may be coupled with one or more switching components configurable for further coupling of the source nodes with the ground node. In some examples, enabling such switching components may add an electrical characteristic (e.g., capacitance) to the conductive path between the source nodes, which may be configurable to mitigate sampling circuitry imbalances.

Abstract: Methods, systems, and devices for signal sampling with offset calibration are described. For example, sampling circuitry may include an input pair of transistors where input signals may be provided to gate nodes of the transistors, and an output signal may be generated based on a comparison of voltages of drain nodes of the transistors. In some examples, source nodes of the transistors may be coupled with each other, such as via a resistance, and each source node may be configured to be coupled with a ground node. In some examples, a conductive path between the source nodes may be coupled with one or more switching components configurable for further coupling of the source nodes with the ground node. In some examples, enabling such switching components may add an electrical characteristic (e.g., capacitance) to the conductive path between the source nodes, which may be configurable to mitigate sampling circuitry imbalances.

Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.

Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal, To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.

Abstract: Disclosed herein is an apparatus that includes a phase frequency detector configured to compare a phase difference between first and second clock signals to generate a phase detection signal, and a slew rate controller configured to lower a slew rate of the first clock signal when a selection signal is in a first state.

Abstract: Disclosed herein is an apparatus that includes a phase frequency detector configured to compare a phase difference between first and second clock signals to generate a phase detection signal, and a slew rate controller configured to lower a slew rate of the first clock signal when a selection signal is in a first state.

Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.

Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.