Patents by Inventor Mani Balakrishnan
Mani Balakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11699993Abstract: Methods, systems, and devices for signal sampling with offset calibration are described. For example, sampling circuitry may include an input pair of transistors where input signals may be provided to gate nodes of the transistors, and an output signal may be generated based on a comparison of voltages of drain nodes of the transistors. In some examples, source nodes of the transistors may be coupled with each other, such as via a resistance, and each source node may be configured to be coupled with a ground node. In some examples, a conductive path between the source nodes may be coupled with one or more switching components configurable for further coupling of the source nodes with the ground node. In some examples, enabling such switching components may add an electrical characteristic (e.g., capacitance) to the conductive path between the source nodes, which may be configurable to mitigate sampling circuitry imbalances.Type: GrantFiled: August 5, 2021Date of Patent: July 11, 2023Assignee: Micron Technology, Inc.Inventors: Martin Brox, Thomas Hein, Mani Balakrishnan
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Publication number: 20220085800Abstract: Methods, systems, and devices for signal sampling with offset calibration are described. For example, sampling circuitry may include an input pair of transistors where input signals may be provided to gate nodes of the transistors, and an output signal may be generated based on a comparison of voltages of drain nodes of the transistors. In some examples, source nodes of the transistors may be coupled with each other, such as via a resistance, and each source node may be configured to be coupled with a ground node. In some examples, a conductive path between the source nodes may be coupled with one or more switching components configurable for further coupling of the source nodes with the ground node. In some examples, enabling such switching components may add an electrical characteristic (e.g., capacitance) to the conductive path between the source nodes, which may be configurable to mitigate sampling circuitry imbalances.Type: ApplicationFiled: August 5, 2021Publication date: March 17, 2022Inventors: Martin Brox, Thomas Hein, Mani Balakrishnan
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Patent number: 11251796Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.Type: GrantFiled: November 16, 2020Date of Patent: February 15, 2022Assignee: Micron Technology, Inc.Inventors: Yasuhiro Takai, Maksim Kuzmenka, Mani Balakrishnan, Martin Brox
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Publication number: 20210075428Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal, To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.Type: ApplicationFiled: November 16, 2020Publication date: March 11, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Yasuhiro Takai, Maksim Kuzmenka, Mani Balakrishnan, Martin Brox
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Publication number: 20210058090Abstract: Disclosed herein is an apparatus that includes a phase frequency detector configured to compare a phase difference between first and second clock signals to generate a phase detection signal, and a slew rate controller configured to lower a slew rate of the first clock signal when a selection signal is in a first state.Type: ApplicationFiled: August 22, 2019Publication date: February 25, 2021Applicant: Micron Technology, Inc.Inventors: Yasuhiro Takai, Martin Brox, Mani Balakrishnan, Maksim Kuzmenka
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Patent number: 10931287Abstract: Disclosed herein is an apparatus that includes a phase frequency detector configured to compare a phase difference between first and second clock signals to generate a phase detection signal, and a slew rate controller configured to lower a slew rate of the first clock signal when a selection signal is in a first state.Type: GrantFiled: August 22, 2019Date of Patent: February 23, 2021Assignee: Micron Technology, Inc.Inventors: Yasuhiro Takai, Martin Brox, Mani Balakrishnan, Maksim Kuzmenka
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Patent number: 10840918Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.Type: GrantFiled: March 28, 2019Date of Patent: November 17, 2020Assignee: Micron Technology, Inc.Inventors: Yasuhiro Takai, Maksim Kuzmenka, Mani Balakrishnan, Martin Brox
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Publication number: 20200313678Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.Type: ApplicationFiled: March 28, 2019Publication date: October 1, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Yasuhiro Takai, Maksim Kuzmenka, Mani Balakrishnan, Martin Brox