Patents by Inventor Manickam E. Kandaswamy

Manickam E. Kandaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6601024
    Abstract: An HDL-based ASIC design is translated from a first RTL description to a second RTL description. The first RTL description describes the HDL-based ASIC design through a first set of modules arranged in a hierarchical manner. Translation includes: creating a reference gate-level netlist by synthesizing the HDL-based ASIC design described using the first RTL description; creating a second set of modules by translating the first RTL description of the first set of modules to the second RTL description module by module; and creating a combined RTL and gate-level design by integrating at least one module from the second set of modules within the reference gate-level netlist. Each module translated into the second RTL description may be also checked for compilation warning or error messages. If any warning or error messages are generated, the offending module(s) is modified to eliminate the warning or error messages.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: July 29, 2003
    Assignee: Synopsys, Inc.
    Inventors: Shivakumar Shankar Chonnad, Thomas Warren Savage, Manickam E. Kandaswamy, Maulin Bhatt, Christopher A. Kopetzky