Abstract: A method for generating a real-time test environment activity view for a functional simulation is disclosed. In some embodiments, the method includes retrieving a unique identifier (ID) associated with each of a plurality of testbench components present in a test environment from a real-time test environment activity viewer log file. The method further includes iteratively fetching from the real-time test environment activity viewer log file, a set of information corresponding to an activity associated with each of the plurality of testbench components based on the associated unique ID. The method further includes contemporaneously generating at each iteration, a real-time test environment activity view for each of the plurality of testbench components based on the associated set of information. The method further includes contemporaneously rendering at each iteration, the real-time test environment activity view for each of the plurality of testbench components via a Graphical User Interface (GUI).

Abstract: A method for generating a simulation timeline encoded packets view is disclosed. In some embodiments, the method includes receiving a type string from each of a plurality of simulation testbench components. The method further includes assigning a unique type code to each of the plurality of simulation testbench components based on the type string. The method further includes iteratively receiving from at least one of the plurality of simulation testbench components, a plurality of data strings along with the corresponding assigned unique type code. The method further includes storing each of the plurality of data strings marked with an associated receipt timestamp. The method further includes contemporaneously generating at each iteration, a simulation timeline encoded packets view for each of the plurality of simulation testbench components. The method further includes contemporaneously rendering at each iteration the simulation timeline encoded packets view via a Graphical User Interface (GUI).

Abstract: This disclosure relates to system and method for generating an encapsulated error signature during functional simulation. The method includes receiving at least one error descriptor notification message from at least one of a plurality of testbench components. Each of the at least one error descriptor notification message includes values corresponding to a plurality of error attributes including error ranking, error code, error message, and error score. The method further includes iteratively updating in real-time, a plurality of arrays based on values corresponding to one or more of the plurality of error attributes, in response to receiving each of the at least one error descriptor notification message. The method further includes iteratively generating in real-time, an encapsulated error signature based on each of the error ranking, the error code, and an error count associated with the error code derived from one or more of the plurality of arrays.

Abstract: A method for managing transactions burstiness associated with a sequence of transactions generated in a test environment for verifying a Device Under Test (DUT) is disclosed. In some embodiments, the method includes processing a plurality of signals associated with a sequence of transactions. The method further includes generating a transactions burstiness signature representative of the sequence of transactions based on processing a set of signals from the plurality of signals. The method further includes analysing the transactions burstiness signature to identify at least one pattern of interest. The method further includes iteratively providing an input comprising at least one missing pattern of interest. The method further includes iteratively generating a subsequent sequence of transactions and a subsequent transactions burstiness signature associated with the subsequent sequence of transactions.

Abstract: This disclosure relates to method and system for representing functional simulation performance for a plurality of simulations in real-time using Graphical User Interface (GUI) elements. For each of the plurality of simulations in a verification environment and upon completing each of a plurality of simulation intervals, the method includes determining a simulation performance value for a simulation interval based on wall clock time lapsed during completion of the simulation interval; calculating, in real-time, an average simulation performance value based on a sum of the simulation performance value corresponding to each of completed simulation intervals from the plurality of simulation intervals; estimating an additional wall clock time required to complete remaining of the plurality of simulation intervals using the average simulation performance value; and updating a special log file with a set of simulation parameters.

Abstract: A method for identifying locked-up simulation testbench components during a simulation is disclosed. In some embodiments, the method includes creating, by an initiator simulation testbench component, at least one migrant packet. The method further includes circulating, during a component identification cycle, each of the at least one migrant packet in an associated predefined direction through each of the plurality of simulation testbench components in the associated daisy loop from the at least one daisy loop. The method further includes circulating, during an issue identification cycle, each of the least one migrant packet in the associated predefined direction through each of the plurality of simulation testbench components in the associated daisy loop.

Abstract: A method for off-loading streams selection to generate organized concurrent streams in a simulation environment is disclosed. In some embodiments, the method includes receiving at least one stream selection request for a DUT from a DUT input generator; performing a stream selection process in response to receiving the request. In order to perform the stream selection process, the method includes analyzing each of a plurality of stream specification entries of a stream specification entries array; selecting a stream from the plurality of streams based on one or more of the set of stream specification entry fields associated with the stream; and generating a stream selection result object based on the selected stream; sending the stream selection result object associated with the selected stream to a respective DUT input generator; and utilizing, by the respective DUT input generator, the stream selection result object associated with the selected stream.

Abstract: The present disclosure relates to system(s) and method(s) for interactively controlling the course of a functional simulation of DUV/SUV. The system comprises a testbench and the DUV/SUV connected to the testbench. The testbench generates a set of input data/packets as a stimulus to be processed by the DUV/SUV. The set of input data/packets is generated to simulate and verify the DUV/SUV. Further, the testbench identifies a pre-defined event at runtime during the simulation. Upon identification of the event, the testbench is configured to pause the simulation and transmit a notification message to a user indicating the occurrence of the event. Further, the testbench waits for a pre-defined time interval to receive one or more user inputs. The testbench further generates new stimulus based on the one or more user inputs and resumes the paused simulation with the new stimulus, thereby controlling the course of the functional simulation.

Abstract: Disclosed is a system for providing an inference associated with delays in processing input data packet(s) by a Design Under Verification (DUV)/System Under Verification (SUV) characterized by maintaining timing information of the input data packet(s) is disclosed. To provide an inference, initially, an input data packet is processed by a DUV or SUV. Simultaneously, an expected data packet corresponding to the input data packet is predicted and a Unique Identifier is assigned to the expected data packet corresponding to the input data packet that entered into the DUV/SUV. After assigning the Unique Identifier, the plurality of data fields pertaining to the Unique Identifier are populated in an array of Packet Timing Entries based on a Delay Identifier (ID) and a Delay Mode. The plurality of data fields may then be used for reporting various delay statistics and operational behaviour of DUV/SUV.

Abstract: Disclosed is a system for providing an inference associated with delays in processing input data packet(s) by a Design Under Verification (DUV)/System Under Verification (SUV) characterized by maintaining timing information of the input data packet(s) is disclosed. To provide an inference, initially, an input data packet is processed by a DUV or SUV. Simultaneously, an expected data packet corresponding to the input data packet is predicted and a Unique Identifier is assigned to the expected data packet corresponding to the input data packet that entered into the DUV/SUV. After assigning the Unique Identifier, the plurality of data fields pertaining to the Unique Identifier are populated in an array of Packet Timing Entries based on a Delay Identifier (ID) and a Delay Mode. The plurality of data fields may then be used for reporting various delay statistics and operational behaviour of DUV/SUV.

Abstract: Disclosed is a system and method for automatically diagnosing an error by performing failure analysis of functional simulation pertaining to a Design Under Verification (DUV) or System Under Verification (SUV). A prediction unit generates a set of expected output packets upon processing a set of input packets' copy. A comparison unit compares an actual output packet, from the set of actual output packets, with an expected output packet, from the set of expected output packets, corresponding to the actual output packet. When there is a mismatch, the actual output packet is compared with at least one subsequent expected output packet until the match is found. The diagnosing unit automatically diagnoses at least one of a packet drop error, an ordering error, an error in routing, by performing a systematic failure analysis and reports a diagnostic information and/or default diagnostic information associated with the error.

Abstract: The present disclosure relates to system(s) and method(s) for generating a functional simulation's progress report simultaneously when the simulation is in progress. The system comprises a testbench and a DUV/SUV connected to the testbench. The testbench generates a set of input data/packets in order to simulate and verify the DUV/SUV. The system is configured to identify one or more components, from a set of components in the testbench. Furthermore, the system receives one or more current progress messages from the one or more components and identifies one or more component Lock-Up conditions based on the processing of the one or more current progress messages and one or more previous progress messages. Further, the system executes one or more actions to resolve the one or more component Lock-Up conditions. Furthermore, the system generates a simulation progress report, simultaneously at runtime, during the simulation.

Abstract: Disclosed is a system and method for automatically diagnosing an error by performing failure analysis of functional simulation pertaining to a Design Under Verification (DUV) or System Under Verification (SUV). A prediction unit generates a set of expected output packets upon processing a set of input packets' copy. A comparison unit compares an actual output packet, from the set of actual output packets, with an expected output packet, from the set of expected output packets, corresponding to the actual output packet. When there is a mismatch, the actual output packet is compared with at least one subsequent expected output packet until the match is found. The diagnosing unit automatically diagnoses at least one of a packet drop error, an ordering error, an error in routing, by performing a systematic failure analysis and reports a diagnostic information and/or default diagnostic information associated with the error.

Abstract: The present disclosure relates to system(s) and method(s) for generating a functional simulation's progress report simultaneously when the simulation is in progress. The system comprises a testbench and a DUV/SUV connected to the testbench. The testbench generates a set of input data/packets in order to simulate and verify the DUV/SUV. The system is configured to identify one or more components, from a set of components in the testbench. Furthermore, the system receives one or more current progress messages from the one or more components and identifies one or more component Lock-Up conditions based on the processing of the one or more current progress messages and one or more previous progress messages. Further, the system executes one or more actions to resolve the one or more component Lock-Up conditions. Furthermore, the system generates a simulation progress report, simultaneously at runtime, during the simulation.

Abstract: The present disclosure relates to system(s) and method(s) for interactively controlling the course of a functional simulation of DUV/SUV. The system comprises a testbench and the DUV/SUV connected to the testbench. The testbench generates a set of input data/packets as a stimulus to be processed by the DUV/SUV. The set of input data/packets is generated to simulate and verify the DUV/SUV. Further, the testbench identifies a pre-defined event at runtime during the simulation. Upon identification of the event, the testbench is configured to pause the simulation and transmit a notification message to a user indicating the occurrence of the event. Further, the testbench waits for a pre-defined time interval to receive one or more user inputs. The testbench further generates new stimulus based on the one or more user inputs and resumes the paused simulation with the new stimulus, thereby controlling the course of the functional simulation.

Abstract: The present disclosure relates to system(s) and method(s) for simulation results analysis and failures debug using a Descriptive Tracking Header. The method may comprise processing a set of input packets by a Design Under Verification or System Under Verification (DUV/SUV) and mimicking, by a prediction unit corresponding to the DUV/SUV, functionality of the DUV/SUV. The prediction unit may be a part of a testbench and is configured to process a set of input packets to predict a set of expected output packets. In one embodiment, each expected output packet from the set of expected output packets may be attached with a Descriptive Tracking Header. The Descriptive Tracking Header corresponds to metadata associated with the expected output packet.

Abstract: The present disclosure relates to system(s) and method(s) for capturing transaction specific stage-wise log data corresponding to at least one of a Design Under Verification or System Under Verification (DUV/SUV). The system comprises a testbench and the DUV/SUV connected to the testbench. The testbench is configured to generate a set of input packets to be processed by the DUV/SUV. Further, the testbench is also configured to generate corresponding expected output packets. If an expected output packet does not match the corresponding actual output packet generated by the DUV/SUV after processing the set of input packets, or if the actual output packet is not generated by the DUV/SUV (when it is expected to), the testbench is configured to capture transaction specific stage-wise log data for the corresponding expected output packet in a separate TSSW log file.

Abstract: The present disclosure relates to system(s) and method(s) for simulation results analysis and failures debug using a Descriptive Tracking Header. The method may comprise processing a set of input packets by a Design Under Verification or System Under Verification (DUV/SUV) and mimicking, by a prediction unit corresponding to the DUV/SUV, functionality of the DUV/SUV. The prediction unit may be a part of a testbench and is configured to process a set of input packets to predict a set of expected output packets. In one embodiment, each expected output packet from the set of expected output packets may be attached with a Descriptive Tracking Header. The Descriptive Tracking Header corresponds to metadata associated with the expected output packet.

Abstract: The present disclosure relates to system(s) and method(s) for capturing transaction specific stage-wise log data corresponding to at least one of a Design Under Verification or System Under Verification (DUV/SUV). The system comprises a testbench and the DUV/SUV connected to the testbench. The testbench is configured to generate a set of input packets to be processed by the DUV/SUV. Further, the testbench is also configured to generate corresponding expected output packets. If an expected output packet does not match the corresponding actual output packet generated by the DUV/SUV after processing the set of input packets, or if the actual output packet is not generated by the DUV/SUV (when it is expected to), the testbench is configured to capture transaction specific stage-wise log data for the corresponding expected output packet in a separate TS SW log file.