Abstract: A semiconductor integrated circuit package incorporating a preformed one-piece mold cap and heatspreader assembly is disclosed. One implementation includes a substrate with a die attached to the substrate. The die is electrically connected with electrical connections formed on the substrate using bonding wires. A preformed one-piece integrated mold cap and heatspreader assembly attached to the substrate to enclose at least a portion of the bonding wires and the die. Methods of assembling semiconductor integrated circuit packages using a preformed one-piece integrated mold cap and heatspreader assembly are also disclosed.

Abstract: A strip on which a plurality of integrated circuit package outlines may be fabricated within a plurality of process tools. The strip includes one or more fiducial notches and/or guide pin notches formed in an outer edge of the strip. The one or more fiducial and/or guide pin notches allow a position of the strip to be identified within at least one process tool of the plurality of process tools. By forming the notches in the outer periphery of the strip, the usable area on the strip on which integrated circuit package outlines may be formed is increased. The strip may alternatively include conventional fiducial and/or guide pin holes, with the molding compound applied at least partially around the holes on one or more sides of the strip. The strip may further alternatively include fiducial holes filled with a translucent material that provides stability to the strip while allowing the strip to be used with an optical recognition sensor.

Abstract: A semiconductor integrated circuit package incorporating a preformed one-piece mold cap and heatspreader assembly is disclosed. One implementation includes a substrate with a die attached to the substrate. The die is electrically connected with electrical connections formed on the substrate using bonding wires. A preformed one-piece integrated mold cap and heatspreader assembly attached to the substrate to enclose at least a portion of the bonding wires and the die. Methods of assembling semiconductor integrated circuit packages using a preformed one-piece integrated mold cap and heatspreader assembly are also disclosed.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate includes at least one electrical ground plane and includes a plurality solder balls formed on a surface thereof. The solder balls include a set of “thermal” solder balls that are positioned near the perimeter of the package and electrically connected with a ground plane of the package. The IC die is electrically connected with the ground plane that is connected with the “thermal” solder balls. A heat spreader is mounted on the package with conductive mounting pegs that are electrically connected with the ground plane. The heat spreader is in thermal communication with the die and also in thermal communication with the set of “thermal” solder balls. This configuration enables a portion of the heat generated by the die to be dissipated from the die through the heat spreader into the set of “thermal” solder balls.

Abstract: A method of forming a photo-resist image on a substrate, such as a conductive film. The method provides that a photo-resist image is printed directly onto the conductive film, such as by using an ink jet printer. Specifically, a CAD image may be sent from a computer to the ink jet printer, and the ink jet printer may use the CAD image to print the photo-resist image. The method may provide that a copper film is applied to a dielectric substrate, and then the photo-resist image is printed directly onto the copper film. Then, at least a portion of the copper film is removed, such as by etching, and at least a portion of the photo-resist image which has been printed on the copper film is removed, such as by etching. By printing the photo-resist image directly onto the copper film, it is not necessary to perform steps such as: applying a mask, exposing to UV light, and developing.

Abstract: A method of shielding an integrated circuit from electromagnetic interference. The integrated circuit is at least partially encapsulated within an electromagnetic interference resistant molding compound, and then the integrated circuit is completely encapsulated within a second molding compound. In this manner, the electromagnetic interference resistant molding compound protects the integrated circuit from electromagnetic interference, while the second molding compound can be selected for properties traditionally desired in a molding compound, such as thermal, electrical insulating, and structural properties. Thus, the integrated circuit according to the present invention can be placed closer to structures, such as power supplies, which produce electromagnetic interference, without experiencing an unacceptable degradation of performance due to the electromagnetic interference caused by the structures.

Abstract: A method of shielding an integrated circuit from electromagnetic interference. The integrated circuit is at least partially encapsulated within an electromagnetic interference resistant molding compound, and then the integrated circuit is completely encapsulated within a second molding compound. In this manner, the electromagnetic interference resistant molding compound protects the integrated circuit from electromagnetic interference, while the second molding compound can be selected for properties traditionally desired in a molding compound, such as thermal, electrical insulating, and structural properties. Thus, the integrated circuit according to the present invention can be placed closer to structures, such as power supplies, which produce electromagnetic interference, without experiencing an unacceptable degradation of performance due to the electromagnetic interference caused by the structures.

Abstract: A method of forming electrically conductive elements on a base layer of an electronic substrate without the use of solder mask. A layer of electrically conductive material is deposited on the base layer, and a first layer of photo imageable ink is applied over the electrically conductive material layer. The first layer of photo imageable ink is patterned to expose portions of the electrically conductive material layer, which are then etched to resolve traces in the electrically conductive material layer. The first layer of photo imageable ink is removed, and a second layer of photo imageable ink is applied over the traces and channels between the traces. The second layer of photo imageable ink is then patterned to expose the traces, and a third layer of photo imageable ink is applied over the traces and the second layer of photo imageable ink. The third layer of photo imageable ink is patterned to expose deposition sites on the traces, within which are formed electrically conductive fingers.

Abstract: An improvement to an integrated circuit package substrate of the type that has a bonding ring with an exposed upper surface, where a first portion of the exposed upper surface is for receiving a molding compound and a second portion of the exposed upper surface is for receiving an electrical connection. A solder mask is formed on the first portion of the exposed upper surface of the bonding ring.

Abstract: A method of forming electrically conductive elements on a base layer of an electronic substrate without the use of solder mask. A layer of electrically conductive material is deposited on the base layer, and a first layer of photo imageable ink is applied over the electrically conductive material layer. The first layer of photo imageable ink is patterned to expose portions of the electrically conductive material layer, which are then etched to resolve traces in the electrically conductive material layer. The first layer of photo imageable ink is removed, and a second layer of photo imageable ink is applied over the traces and channels between the traces. The second layer of photo imageable ink is then patterned to expose the traces, and a third layer of photo imageable ink is applied over the traces and the second layer of photo imageable ink. The third layer of photo imageable ink is patterned to expose deposition sites on the traces, within which are formed electrically conductive fingers.

Abstract: A method of forming a photo-resist image on a substrate, such as a conductive film. The method provides that a photo-resist image is printed directly onto the conductive film, such as by using an ink jet printer. Specifically, a CAD image may be sent from a computer to the ink jet printer, and the ink jet printer may use the CAD image to print the photo-resist image. The method may provide that a copper film is applied to a dielectric substrate, and then the photo-resist image is printed directly onto the copper film. Then, at least a portion of the copper film is removed, such as by etching, and at least a portion of the photo-resist image which has been printed on the copper film is removed, such as by etching. By printing the photo-resist image directly onto the copper film, it is not necessary to perform steps such as: applying a mask, exposing to UV light, and developing.

Abstract: An improvement to an integrated circuit package substrate of the type that has a bonding ring with an exposed upper surface, where a first portion of the exposed upper surface is for receiving a molding compound and a second portion of the exposed upper surface is for receiving an electrical connection. A solder mask is formed on the first portion of the exposed upper surface of the bonding ring.

Abstract: A package substrate having sides, which is formed of multiple non electrically conductive layers laminated together. Each of the multiple non electrically conductive layers is formed of a first lamina and a second lamina bonded together in a resin matrix. The first lamina is formed of woven fibers having a first warp. The first warp of the first lamina is disposed at a positive orientation of a first angle from the sides of the package substrate, where the first angle is neither zero degrees nor ninety degrees. The second lamina is also formed of woven fibers, having a second warp. The second warp of the second lamina is disposed at a negative orientation of the first angle from the sides of the package substrate. Electrically conductive layers are dispersed between different ones of the multiple non electrically conductive layers, with electrical connections dispersed between different ones of the electrically conductive layers.

Abstract: A method of forming a via in a circuit, such that parasitic capacitance is reduced. The surface layers of the circuit are identified, to which continuity with the via is desired, and secondary layers of the circuit are also identified. Via lands are formed only on the surface layers and not on the secondary layers. The via lands are formed in first portions of the surface layers, where the via is to pass through the surface layers. Nonconductive cut outs are formed in second portions of the secondary layers where the via is to pass through the secondary layers. The surface layers and the secondary layers of the circuit are laminated together. The first portions of the surface layers are aligned with the second portions of the secondary layers. A through hole is formed through the via lands formed in the surface layers, and also through the cut outs formed in the secondary layers. The via is formed in the through hole.

Abstract: An apparatus and method are presented for testing an adhesive layer formed between an integrated circuit and a plate, wherein the plate may be semiconductor device package substrate or a heat spreader. The apparatus includes a pull stud and a pull arm. The pull stud has an upper portion and a lower portion, wherein the lower portion is attached to a surface of the integrated circuit opposite the plate. The upper portion of the pull stud may be, for example, a tapered cylinder having a large end and a small end. The small end meets the lower portion of the pull stud. The pull arm has two opposed ends and at least one bracket for receiving a force. One of the pull arm ends has a "V"-shaped opening surrounded by a lip which receives the upper portion of the pull stud. During use, the lip contacts and retains the upper portion of the pull stud. The opening has an upper wall, and an upper surface of the pull stud contacts the upper wall when the upper portion of the pull stud is inserted into the opening.

Abstract: A semiconductor chip fabrication assembly and method including a semiconductor package having a packaging substrate and a semiconductor die. An active circuit surface of the semiconductor die is positioned adjacent to a contact surface of the packaging substrate such that a substantially thin gap is formed therebetween. A semi-rigid shroud device is provided which defines a vacuum chamber configured to extend around the gap to hermetically seal the gap within the vacuum chamber. A dispensing device is provided having an outlet end positioned proximate the gap in the vacuum chamber which is adapted to vacuum flow the bonding material between the electrical contacts in the gap, and between the active circuit surface and the contact surface. The absence of air and any other gases forms a substantially voidless underfill layer of bonding material in the gap.

Abstract: An Integrated Circuit (IC) wafer test fixture includes a baseplate and a top plate. During testing, an IC wafer is positioned between the baseplate and top plate with annular rubber gaskets, forming sealed cavities above and below the IC wafer. A fluid pressure generator with a pressure gauge inserts a fluid under pressure into one of the cavities, causing the IC wafer to be subject to stress. The fluid distributes a uniform pressure load on the surface of the IC wafer. The pressure of the fluid may be gradually increased until a desired pressure is obtained or the wafer fails. The pressure at failure is recorded, and by calculation the failure stress of the IC wafer can be determined. A second embodiment of the test fixture includes a pressure vessel with a threaded sealed opening at the top and a stepped sealed opening at the bottom. The inner diameter of the insert is sized for an IC wafer. In use, the IC wafer is positioned on top of the insert, and the pressure vessel is sealed.

Abstract: A stiffener device for use with a flip chip packaging assembly including a generally rectangular, plate-like member having a substantially uniform thickness. At each of the rectangular plate-like member is a curved chamfer portion extending from an upper surface to a lower surface thereof, and defined by a chamfer edge commencing at one side edge forming the respective corner and terminating at an opposite side edge of the respective corner. Each curved chamfer portion is adapted to receptively accommodate a respective mounting bolt therethrough. The fabrication of the stiffener device is formed from a single stamping or punching operation in a manner maintaining a substantially planar upper surface and lower surface.

Abstract: According to the present invention, a semiconductor package is provided. In one version of the invention, the semiconductor package includes a laminated substrate having a semiconductor die mounted on its upper surface, electrical connections between bond pads on the semiconductor die and conductive traces on the substrate, as well as electrical connections between the conductive traces and electrical contacts on the lower surface of the substrate. The semiconductor package also includes a molded covering on the upper surface of the substrate which covers the semiconductor die and the electrical connections. The molded covering has a mold body portion and a mold gate runner which extends from the mold body portion to an edge of the substrate. The mold gate runner is provided with a surface that is substantially even with the edge of the substrate and rises perpendicularly from the upper surface of the substrate.