Abstract: Various example embodiments relate to computation of a shared exponent for numbers. A plurality of bit vectors may be obtained. A bitwise OR-operation may be performed for the plurality of bit vectors to obtain an auxiliary bit vector. The shared exponent may be then determined based on a position of a most significant bit having value equal to one in the auxiliary bit vector. The representation for the plurality of bit vectors may be then determined based on the shared exponent. Apparatuses, methods, and computer programs are disclosed.

Abstract: An apparatus for processing a received radio signal includes at least one processor and at least one memory. The at least one memory storing computer program code. The at least one memory and the computer program code being configured to, with the at least one processor, cause the apparatus to at least in part perform processing (received radio signal data with first and second signal processing chains, which respectively include first and second processing modules configured to respectively determine first output and an estimation of the first output data, and determine second output data using a neural network based on the estimation; updating parameters of the neural network based on the first output data and the second output data; and after the updating, processing the received radio signal data with the second signal processing chain, without applying the first processing module.

Abstract: An apparatus for processing a received radio signal includes at least one processor and at least one memory. The at least one memory storing computer program code. The at least one memory and the computer program code being configured to, with the at least one processor, cause the apparatus to at least in part perform processing (received radio signal data with first and second signal processing chains, which respectively include first and second processing modules configured to respectively determine first output and an estimation of the first output data, and determine second output data using a neural network based on the estimation; updating parameters of the neural network based on the first output data and the second output data; and after the updating, processing the received radio signal data with the second signal processing chain, without applying the first processing module.

Abstract: Apparatus and method for symbol detection are disclosed. The solution comprises obtaining (400) multiple-input-multiple-output symbols received over a transmission channel, the symbols comprising a plurality of layers, each layer comprising a constellation point of multiple candidate constellation points, selecting (402) for each layer a precision, each layer having a precision smaller or equal than the precision of a previous layer and searching (404) for each layer, utilising the selected precision, the constellation point among the candidate constellation points by minimising a given cost function, utilising a plurality of Arithmetic and Logic Units, ALUs, comprising at least one real and imaginary part, the ALUs of the apparatus comprising real and imaginary part having different precisions by having different number of bits, the data memory and the plurality of ALUs being connected with each other by a data bus of a given width.

Abstract: Apparatus and method for symbol detection are disclosed. The solution comprises obtaining (400) multiple-input-multiple-output symbols received over a transmission channel, the symbols comprising a plurality of layers, each layer comprising a constellation point of multiple candidate constellation points, selecting (402) for each layer a precision, each layer having a precision smaller or equal than the precision of a previous layer and searching (404) for each layer, utilising the selected precision, the constellation point among the candidate constellation points by minimising a given cost function, utilising a plurality of Arithmetic and Logic Units, ALUs, comprising at least one real and imaginary part, the ALUs of the apparatus comprising real and imaginary part having different precisions by having different number of bits, the data memory and the plurality of ALUs being connected with each other by a data bus of a given width.