Patents by Inventor Manippady Krishna KUMAR

Manippady Krishna KUMAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device fabrication
    Patent number: 9972709
    Abstract: There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a first and a second nucleation layer on a substrate; depositing a binary layer over these nucleation layers; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge and their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: May 15, 2018
    Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Lakshmi Kanta Bera, Surani Bin Dolmanan, Manippady Krishna Kumar, Rasanayagam Sivasayan Kajen, Sudhiranjan Tripathy
  • Semiconductor device fabrication
    Patent number: 9954088
    Abstract: There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a nucleation layer on a substrate; depositing a binary layer over the nucleation layer; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge or their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: April 24, 2018
    Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Lakshmi Kanta Bera, Surani Bin Dolmanan, Manippady Krishna Kumar, Rasanayagam Sivasayan Kajen, Sudhiranjan Tripathy
  • SEMICONDUCTOR DEVICE FABRICATION
    Publication number: 20170222030
    Abstract: There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a first and a second nucleation layer on a substrate; depositing a binary layer over these nucleation layers; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge and their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.
    Type: Application
    Filed: April 4, 2017
    Publication date: August 3, 2017
    Inventors: Lakshmi Kanta Bera, Surani Bin Dolmanan, Manippady Krishna Kumar, Rasanayagam Sivasayan Kajen, Sudhiranjan Tripathy
  • SEMICONDUCTOR DEVICE FABRICATION
    Publication number: 20160233325
    Abstract: There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a nucleation layer on a substrate; depositing a binary layer over the nucleation layer; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge or their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.
    Type: Application
    Filed: October 20, 2014
    Publication date: August 11, 2016
    Inventors: Lakshmi Kanta BERA, Surani Bin DOLMANAN, Manippady Krishna KUMAR, Rasanayagam Sivasayan KAJEN, Sudhiranjan TRIPATHY