Patents by Inventor Manish Biyani
Manish Biyani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10294472Abstract: The present invention relates to a nucleic acid linker for producing a complex of mRNA, and a protein or a peptide which is encoded by the mRNA, the linker comprising: a spacer portion at the 5?-terminal; a polynucleotide portion hybridizable with at least a part of a sequence of the mRNA; and an arm portion which has a connection portion for the protein or the peptide at the 3?-terminal, in which the spacer portion, the polynucleotide portion, and the arm portion form a single strand, and in which the polynucleotide portion contains a photoreactive base derivative.Type: GrantFiled: September 10, 2015Date of Patent: May 21, 2019Assignees: THE UNIVERSITY OF TOKYO, NIKON CORPORATIONInventors: Takanori Ichiki, Shingo Ueno, Manish Biyani, Ryo Kobayashi, Hirofumi Shiono
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Patent number: 9844764Abstract: The present invention relates to a protein or peptide printing method, comprising (a) a step for preparing nucleic acids and a cell-free protein synthesis system in an engraved plate composed of microscopic grooves having a specific opening shape, (b) a step for superimposing a substrate on the engraved plate so as to contact a protein or peptide to be synthesized in the microscopic grooves, and (c) a step for synthesizing the protein or peptide from the nucleic acids using the cell-free protein synthesis system in the microscopic grooves, and immobilizing the protein or peptide on the substrate along the specific opening shapes of the microscopic grooves.Type: GrantFiled: February 21, 2013Date of Patent: December 19, 2017Assignees: University of Tokyo, Nikon CorporationInventors: Takanori Ichiki, Manish Biyani, Hirofumi Shiono
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Publication number: 20160076022Abstract: The present invention relates to a nucleic acid linker for producing a complex of mRNA, and a protein or a peptide which is encoded by the mRNA, the linker comprising: a spacer portion at the 5?-terminal; a polynucleotide portion hybridizable with at least a part of a sequence of the mRNA; and an arm portion which has a connection portion for the protein or the peptide at the 3?-terminal, in which the spacer portion, the polynucleotide portion, and the arm portion form a single strand, and in which the polynucleotide portion contains a photoreactive base derivative.Type: ApplicationFiled: September 10, 2015Publication date: March 17, 2016Applicants: The University of Tokyo, Nikon CorporationInventors: Takanori Ichiki, Shingo Ueno, Manish Biyani, Ryo Kobayashi, Hirofumi Shiono
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Patent number: 8592348Abstract: A method for producing a chip on which biomolecules are immobilized in an aligned state, comprises (a) producing a substrate 1 on which a plurality of biomolecules 1 of a single type are immobilized in an aligned state, (b) adding reaction reagents for synthesizing biomolecules 2 to microreactors on a microreactor chip comprising the microreactors at positions overlapping with the sequence positions of the biomolecules 1 immobilized on the substrate 1 produced in step (a), (c) closely attaching the microreactor chip to the substrate 1 so that the reaction reagents for synthesizing the biomolecules 2 are allowed to come into contact with the biomolecules 1, so as to synthesize the biomolecules 2 in the microreactors, and (d) superposing the microreactor chip on a substrate 2 after completion of step (c) so as to bind the biomolecules 2 onto the substrate 2; and a chip produced thereby.Type: GrantFiled: November 1, 2007Date of Patent: November 26, 2013Assignee: Japan Science and Technology AgencyInventors: Naoto Nemoto, Takanori Ichiki, Manish Biyani
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Publication number: 20130237430Abstract: The present invention relates to a protein or peptide printing method, comprising (a) a step for preparing nucleic acids and a cell-free protein synthesis system in an engraved plate composed of microscopic grooves having a specific opening shape, (b) a step for superimposing a substrate on the engraved plate so as to contact a protein or peptide to be synthesized in the microscopic grooves, and (c) a step for synthesizing the protein or peptide from the nucleic acids using the cell-free protein synthesis system in the microscopic grooves, and immobilizing the protein or peptide on the substrate along the specific opening shapes of the microscopic grooves.Type: ApplicationFiled: February 21, 2013Publication date: September 12, 2013Applicant: The University of TokyoInventors: Takanori Ichiki, Manish Biyani, Hirofumi Shiono
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Patent number: 8445413Abstract: The present invention provides a linker preferably used when constructing an mRNA/cDNA-puromycin-protein conjugate used in an in vitro virus method, and an mRNA/cDNA-puromycin-protein conjugate constructed using that linker. More specifically, the present invention provides a linker for ligating mRNA and puromycin or a puromycin-like compound to construct an mRNA/cDNA-puromycin-protein conjugate, the linker comprising a single-stranded RNA as a main backbone, and having, in this main backbone, a solid phase binding site for binding an mRNA-puromycin-protein conjugate to a solid phase site, and a pair of cleavage sites provided at locations surrounding the solid phase binding site; an mRNA-puromycin-protein conjugate constructed using this linker; an mRNA bead or an mRNA chip comprising this conjugate; a protein chip produced from this mRNA chip; and a diagnostic kit using the mRNA bead or the mRNA chip.Type: GrantFiled: October 12, 2005Date of Patent: May 21, 2013Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Naota Nemoto, Manish Biyani
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Patent number: 7982514Abstract: A system for storing state values during standby mode operation comprises a master flip flop that receives and stores state information during active mode operation and an associated slave flip flop that receives and stores state information during active mode and standby mode operation. The system further comprises a standby mode control circuit to control the state of the master and slave flip flops during active and standby mode operation based on at least two control signals. A first transfer gate determines the current flow to and from the master flip flop based on the output of the standby mode control circuit. Similarly, a second transfer gate determines current flow to and from the slave flip flop based on the output of the standby mode control circuit. A first power supply powers the master flip flop during active mode operation.Type: GrantFiled: June 23, 2010Date of Patent: July 19, 2011Assignee: Marvell International Ltd.Inventor: Manish Biyani
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Publication number: 20100259309Abstract: A system for storing state values during standby mode operation comprises a master flip flop that receives and stores state information during active mode operation and an associated slave flip flop that receives and stores state information during active mode and standby mode operation. The system further comprises a standby mode control circuit to control the state of the master and slave flip flops during active and standby mode operation based on at least two control signals. A first transfer gate determines the current flow to and from the master flip flop based on the output of the standby mode control circuit. Similarly, a second transfer gate determines current flow to and from the slave flip flop based on the output of the standby mode control circuit. A first power supply powers the master flip flop during active mode operation.Type: ApplicationFiled: June 23, 2010Publication date: October 14, 2010Inventor: Manish BIYANI
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Patent number: 7796445Abstract: A device can include 1) a sustained or constantly powered low leakage latch to and from which a volatile state is uploaded and downloaded, respectively, based on an active-to-low signal, and 2) an intermittently powered or de-powerable memory element, coupled to the low leakage latch, from which and to which the volatile state is uploaded and downloaded, respectively, based on the active-to-low signal and a de-powerable voltage across the de-powerable memory element is powered and un-powered, respectively.Type: GrantFiled: February 12, 2008Date of Patent: September 14, 2010Assignee: Marvell International, Ltd.Inventors: Manish Biyani, Franco Ricci
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Patent number: 7768331Abstract: A system for storing state values during standby mode operation comprises a master flip flop that receives and stores state information during active mode operation and an associated slave flip flop that receives and stores state information during active mode and standby mode operation. The system further comprises a standby mode control circuit to control the state of the master and slave flip flops during active and standby mode operation based on at least two control signals. A first transfer gate determines the current flow to and from the master flip flop based on the output of the standby mode control circuit. Similarly, a second transfer gate determines current flow to and from the slave flip flop based on the output of the standby mode control circuit. A first power supply powers the master flip flop during active mode operation.Type: GrantFiled: January 23, 2008Date of Patent: August 3, 2010Assignee: Marvell International Ltd.Inventor: Manish Biyani
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Publication number: 20100035769Abstract: It is an object of the present invention to provide a method for producing a biomolecule assay chip using a microreactor technique, and a chip produced by the method.Type: ApplicationFiled: November 1, 2007Publication date: February 11, 2010Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Naoto Nemoto, Takanori Ichiki, Manish Biyani
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Publication number: 20080312103Abstract: The present invention provides a linker preferably used when constructing an mRNA/cDNA-puromycin-protein conjugate used in an in vitro virus method, and an mRNA/cDNA-puromycin-protein conjugate constructed using that linker. More specifically, the present invention provides a linker for ligating mRNA and puromycin or a puromycin-like compound to construct an mRNA/cDNA-puromycin-protein conjugate, the linker comprising a single-stranded RNA as a main backbone, and having, in this main backbone, a solid phase binding site for binding an mRNA-puromycin-protein conjugate to a solid phase site, and a pair of cleavage sites provided at locations surrounding the solid phase binding site; an mRNA-puromycin-protein conjugate constructed using this linker; an mRNA bead or an mRNA chip comprising this conjugate; a protein chip produced from this mRNA chip; and a diagnostic kit using the mRNA bead or the mRNA chip.Type: ApplicationFiled: October 12, 2005Publication date: December 18, 2008Inventors: Naoto Nemoto, Manish Biyani
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Publication number: 20080214783Abstract: The present invention provides a protein synthesis method for efficiently synthesizing a desired protein so that it is properly folded so as to demonstrate a function thereof, the method comprising contacting a translation system with a solid phase-immobilized mRNA in which mRNA encoding that protein is immobilized on a solid phase, a protein synthesis apparatus for the method or the like. The protein synthesis method, protein synthesis apparatus or the like of the present invention are useful for, for example, large-volume synthesis of useful proteins.Type: ApplicationFiled: November 11, 2005Publication date: September 4, 2008Inventors: Naoto Nemoto, Manish Biyani
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Patent number: 6775180Abstract: An integrated circuit having a state retentive memory structure to store state values. A high performance section uses thin gate-oxide transistors and the state retentive memory structure uses thick gate-oxide transistors to capture and retain the state values when operating in a low power mode.Type: GrantFiled: December 23, 2002Date of Patent: August 10, 2004Assignee: Intel CorporationInventors: Manish Biyani, Lawrence T. Clark, Shay P. Demmons, Franco Ricci
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Publication number: 20040120182Abstract: An integrated circuit having a state retentive memory structure to store state values. A high performance section uses thin gate-oxide transistors and the state retentive memory structure uses thick gate-oxide transistors to capture and retain the state values when operating in a low power mode.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Inventors: Manish Biyani, Lawrence T. Clark, Shay P. Demmons, Franco Ricci