Patents by Inventor Manish Chandra Joshi

Manish Chandra Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High performance two-port SRAM architecture using 8T high performance single port bit cell
    Patent number: 8958254
    Abstract: An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read operation during a first clock cycle state. A write address flip-flop/clock circuit receives the clock signal and the write address signals and initiates a write operation during a second clock cycle state. An inverter receives and inverts the clock signal and applies the inverted clock signal to the write address flip-flop/clock circuit. The read address latch/clock circuit initiates a read word line precharge operation during the second clock cycle state and a write word line precharge operation during the first clock cycle state. The write address flip-flop/clock circuit may also include a loose self-timer to end a write cycle is a clock signal continues beyond a predetermined time.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: February 17, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Manish Chandra Joshi, Parvinder Kumar Rana, Lakshmikantha Vakwadi Holla
  • HIGH PERFORMANCE TWO-PORT SRAM ARCHITECTURE USING 8T HIGH PERFORMANCE SINGLE-PORT BIT CELL
    Publication number: 20130215689
    Abstract: An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read operation during a first clock cycle state. A write address flip-flop/clock circuit receives the clock signal and the write address signals and initiates a write operation during a second clock cycle state. An inverter receives and inverts the clock signal and applies the inverted clock signal to the write address flip-flop/clock circuit. The read address latch/clock circuit initiates a read word line precharge operation during the second clock cycle state and a write word line precharge operation during the first clock cycle state. The write address flip-flop/clock circuit may also include a loose self-timer to end a write cycle is a clock signal continues beyond a predetermined time.
    Type: Application
    Filed: February 22, 2012
    Publication date: August 22, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Manish Chandra Joshi, Parvinder Kumar Rana, Lakshmikantha Vakwadi Holla