Patents by Inventor Manish Dubey
Manish Dubey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210013117Abstract: Embodiments may relate to a microelectronic package that includes a lid coupled with a package substrate such that a die is positioned between the lid and the package substrate. The lid may include a heating element that is to heat an area between the lid and the die. Other embodiments may be described or claimed.Type: ApplicationFiled: July 8, 2019Publication date: January 14, 2021Applicant: Intel CorporationInventors: Peng Li, Kelly P. Lofgreen, Manish Dubey, Bamidele Daniel Falola, Ken Hackenberg, Shenavia S. Howell, Sergio Antonio Chan Arguedas, Yongmei Liu, Deepak Goyal
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Publication number: 20200411407Abstract: Disclosed herein are integrated circuit (IC) packages with solder thermal interface materials (STIM), as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a lid, a die between the package substrate and the lid, and a STIM between the die and the lid. The STIM may have a thickness that is less than 200 microns.Type: ApplicationFiled: June 26, 2019Publication date: December 31, 2020Applicant: Intel CorporationInventors: Manish Dubey, Sergio Antonio Chan Arguedas
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Publication number: 20200395269Abstract: Disclosed herein are channeled lids for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a die between a lid and a package substrate. A bottom surface of the lid may include a channel that at least partially overlaps the die.Type: ApplicationFiled: June 11, 2019Publication date: December 17, 2020Applicant: Intel CorporationInventors: Manish Dubey, Amitesh Saha, Marco Aurelio Cartas, Peng Li, Bamidele Daniel Falola
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Publication number: 20200227332Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.Type: ApplicationFiled: January 10, 2019Publication date: July 16, 2020Applicant: Intel CorporationInventors: Kumar Abhishek Singh, Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Manish Dubey, Ravindranath Mahajan, Ram Viswanath, James C. Matayabas, JR.
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Patent number: 10651108Abstract: Devices and methods disclosed herein can include a conductive foam having pores disposed within the conductive foam. The conductive foam can be compressible between an uncompressed thickness and a compressed thickness. The compressed thickness can be ninety-five percent or less of the uncompressed thickness. In one example, a filler can be disposed in the pores of the conductive foam. The filler can include a first thermal conductivity. The first thermal conductivity can be greater than a thermal conductivity of air.Type: GrantFiled: June 29, 2016Date of Patent: May 12, 2020Assignee: Intel CorporationInventors: Zhizhong Tang, Syadwad Jain, Wei Hu, Michael A. Schroeder, Rajen S. Sidhu, Carl L. Deppisch, Patrick Nardi, Kelly P. Lofgreen, Manish Dubey
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Patent number: 10535615Abstract: An electronic package that includes a substrate and a die attached to the substrate. The electronic package further includes a stiffener that is attached to the substrate adjacent to the die. The stiffener is formed of a first layer made from one material and a second layer made from a different material.Type: GrantFiled: February 12, 2016Date of Patent: January 14, 2020Assignee: Intel CorporationInventors: Manish Dubey, Srikant Nekkanty, Rajendra C. Dias, Patrick Nardi
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Publication number: 20200006273Abstract: A microelectronic device is formed including two or more structures physically and electrically engaged with one another through coupling of conductive features on the two structures. The conductive features may be configured to be tolerant of bump thickness variation in either of the structures. Such bump thickness variation tolerance can result from a contact structure on a first structure including a protrusion configured to extend in the direction of the second structure and to engage a deformable material on that second structure.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Inventors: Manish Dubey, Kousik Ganesan, Suddhasattwa Nad, Thomas Heaton, Sri Chaitra Jyotsna Chavali, Amruthavalli Pallavi Alur
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Patent number: 10206277Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for gradient encapsulant protection of devices in stretchable electronic. For instance, in accordance with one embodiment, there is an apparatus with an electrical device on a stretchable substrate; one or more stretchable electrical interconnects coupled with the electrical device; one or more electrical components electrically coupled with the electrical device via the one or more stretchable electrical interconnects; and a gradient encapsulating material layered over and fully surrounding the electrical device and at least a portion of the one or more stretchable electrical interconnects coupled thereto, in which the gradient encapsulating material has an elastic modulus greater than the stretchable substrate and in which the elastic modulus of the gradient encapsulating material is less than the electrical device. Other related embodiments are disclosed.Type: GrantFiled: December 18, 2015Date of Patent: February 12, 2019Assignee: Intel CorporationInventors: Rajendra C. Dias, Manish Dubey, Tatyana N. Andryushchenko, Aleksandar Aleksov, David W. Staines
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Publication number: 20180357150Abstract: A computer based electronic device emulation and development system includes examining a target platform program and determining a first memory location utilized by the target platform program, and providing a first software object to a host program containing a function that allows access to the first memory location.Type: ApplicationFiled: June 7, 2018Publication date: December 13, 2018Inventors: Ashok Kumar Chaubey, DEVENDER NATH MAURYA, Devender Pal Sharma, Jonathan Torkelson, Manish Dubey, NICHOLAS WESLEY VINYARD
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Publication number: 20180283845Abstract: An interferometer for characterizing a sample, the interferometer including a light emitter to produce a light beam. A wavelength modulator can dither a wavelength of the light beam to produce an input beam having an oscillating wavelength. A beam splitter can be configured to divide the input beam into a reference beam and a measurement beam. The reference beam can reflect from a mirror having a fixed position and return to the beam splitter. The measurement beam can reflect from the sample and return to the beam splitter. The beam splitter can interfere the received reference beam and measurement beam to form an output beam. A detector can convert the output beam to an electrical signal. A processor can control the wavelength modulator, receive the electrical signal, and determine a distance to the sample based on the electrical signal and the oscillating wavelength of the input beam.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Inventors: Mario Pacheco, Manish Dubey, Purushotham Kaushik Muthur Srinath, Deepak Goyal, Liwen Jin
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Patent number: 9887104Abstract: Some embodiments relate to an electronic package. The electronic package includes a substrate and a die attached to the substrate. The electronic package further includes an underfill positioned between the die and the substrate due to capillary action. A support surrounds the die. The support provides the same beneficial fillet geometry on all die edges. Therefore, the support provides similar stress reduction on all die edges. Other embodiments relate to method of fabricating an electronic package. The method includes attaching a die to a substrate and inserting an underfill between the die and the substrate using capillary action. The method further includes placing a support around the die such that the support surrounds the die.Type: GrantFiled: July 3, 2014Date of Patent: February 6, 2018Assignee: Intel CorporationInventors: Manish Dubey, Rajendra C. Dias, Patrick Nardi, David Woodhams
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Publication number: 20180033741Abstract: An electronic package that includes a substrate and a die attached to the substrate. The electronic package further includes a stiffener that is attached to the substrate adjacent to the die. The stiffener is formed of a first layer made from one material and a second layer made from a different material.Type: ApplicationFiled: February 12, 2016Publication date: February 1, 2018Inventors: Manish Dubey, Srikant Nekkanty, Rajendra C. Dias, Patrick Nardi
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Patent number: 9721906Abstract: An electronic package that includes a substrate and a die attached to the substrate. A plurality of supports attached to the substrate adjacent to the die. At least one support in the plurality of supports is positioned adjacent to at least one corner of the die such that the at least one corner of the die is positioned adjacent to the at least one support. Other example forms relate to a method of fabricating an electronic package. The method includes securing a die to a substrate and securing a plurality of supports to the substrate such that at least one support is adjacent to at least one corner of the die.Type: GrantFiled: August 31, 2015Date of Patent: August 1, 2017Assignee: Intel CorporationInventors: Manish Dubey, Rajendra C. Dias, Baris Bicen, Digvijay Raorane, Bharat P. Penmecha
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Publication number: 20170181275Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for gradient encapsulant protection of devices in stretchable electronic. For instance, in accordance with one embodiment, there is an apparatus with an electrical device on a stretchable substrate; one or more stretchable electrical interconnects coupled with the electrical device; one or more electrical components electrically coupled with the electrical device via the one or more stretchable electrical interconnects; and a gradient encapsulating material layered over and fully surrounding the electrical device and at least a portion of the one or more stretchable electrical interconnects coupled thereto, in which the gradient encapsulating material has an elastic modulus greater than the stretchable substrate and in which the elastic modulus of the gradient encapsulating material is less than the electrical device. Other related embodiments are disclosed.Type: ApplicationFiled: December 18, 2015Publication date: June 22, 2017Inventors: Rajendra C. Dias, Manish Dubey, Tatyana N. Andryushchenko, Aleksandar Aleksov, David W. Staines
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Patent number: 9632919Abstract: An example request change tracker may be used to create, modify, monitor, and report events occurring within a development and testing pipeline with respect to one or more computing applications. A request change tracker may include a pipeline event detector, a testing stage detector, a control module, and a reporting module. The pipeline event detector detects a pipeline event indicative of a status of a code module with respect to a pipeline. The testing stage detector determines the associated testing stage in the pipeline, based on the pipeline event. The control module initiates actions with respect to the pipeline, based on the determined testing stage. The reporting module updates a reporting log with information related to the state, progress and results of a testing stage in the pipeline.Type: GrantFiled: September 30, 2013Date of Patent: April 25, 2017Assignee: LinkedIn CorporationInventors: Manish Dubey, Daniel L. Grillo, Sean Keenan, Scott Holmes
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Publication number: 20170062356Abstract: An electronic package that includes a substrate and a die attached to the substrate. A plurality of supports attached to the substrate adjacent to the die. At least one support in the plurality of supports is positioned adjacent to at least one corner of the die such that the at least one corner of the die is positioned adjacent to the at least one support. Other example forms relate to a method of fabricating an electronic package. The method includes securing a die to a substrate and securing a plurality of supports to the substrate such that at least one support is adjacent to at least one corner of the die.Type: ApplicationFiled: August 31, 2015Publication date: March 2, 2017Inventors: Manish Dubey, Rajendra C. Dias, Baris Bicen, Digvijay Raorane, Bharat P. Penmecha
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Publication number: 20170018525Abstract: A method for attaching an integrated circuit (IC) to an IC package substrate includes forming a solder bump on a bond pad of an IC die, forming a solder-wetting protrusion on a bond pad of an IC package substrate, and bonding the solder bump of the IC die to the solder-wetting protrusion of the IC package substrate.Type: ApplicationFiled: March 28, 2014Publication date: January 19, 2017Inventors: Rajendra C. Dias, Manish Dubey, Emre Armagan
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Patent number: 9508660Abstract: A microelectronic die may be formed with chamfer corners for reducing stresses which can lead to delamination and/or cracking failures when such a microelectronic die is incorporated into a microelectronic package. In one embodiment, a microelectronic die may include at least one substantially planar chamfering side extending between at least two adjacent sides of a microelectronic die. In another embodiment, a microelectronic die may include at least one substantially curved or arcuate chamfering side extending between at least two adjacent sides of a microelectronic die.Type: GrantFiled: February 10, 2015Date of Patent: November 29, 2016Assignee: Intel CorporationInventors: Manish Dubey, Emre Armagan, Rajendra C. Dias, Lars D. Skoglund
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Publication number: 20160343591Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.Type: ApplicationFiled: August 1, 2016Publication date: November 24, 2016Inventors: Suriyakala Ramalingam, Manish Dubey, Hsin-Yu Li, Michelle S. Phen-Givoni, Hitesh Arora, Nisha Ananthakrishnan, Yiqun Bai, Yonghao Xiu, Rajendra C. Dias
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Patent number: 9431274Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.Type: GrantFiled: December 20, 2012Date of Patent: August 30, 2016Assignee: Intel CorporationInventors: Suriyakala Ramalingam, Manish Dubey, Hsin-Yu Li, Michelle S. Phen, Hitesh Arora, Nisha Ananthakrishnan, Yiqun Bai, Yonghao Xiu, Rajendra C. Dias