Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.

Abstract: Radio transceiver control interfaces are provided herein. In certain embodiments, a semiconductor die includes a group of transmitters and a group of receivers that operate as a transceiver. Additionally, a group of common pins are used to control settings of both the transmitters and receivers. In one example, data received on the common pins can be used to establish enable settings for each of the transmitters and receivers. Thus, rather than using a one-to-one correspondence between a pin and the setting of a particular transmitter or receiver, a mapping is used between the common pins and the settings of the transmitters and receivers.

Abstract: Devices exchange control signals with each other to ensure proper operation of an overall system. For instance, in a communication system, a baseband processor and a transceiver communicate with each other to exchange information for controlling the respective signal processing parts of the baseband processor and the transceiver. While Serial Peripheral Interfaces (SPIs) can be used, SPI can be extremely slow, and does not provide a protocol for allowing a complex set of control signals to be exchanged between the baseband processor and transceiver. The present disclosure describes a fast control interface which can support various modes of operation in allowing two devices to communicate with each other quickly and effectively.

Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.

Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.

Abstract: Radio transceiver control interfaces are provided herein. In certain embodiments, a semiconductor die includes a group of transmitters and a group of receivers that operate as a transceiver. Additionally, a group of common pins are used to control settings of both the transmitters and receivers. In one example, data received on the common pins can be used to establish enable settings for each of the transmitters and receivers. Thus, rather than using a one-to-one correspondence between a pin and the setting of a particular transmitter or receiver, a mapping is used between the common pins and the settings of the transmitters and receivers.

Abstract: Devices exchange control signals with each other to ensure proper operation of an overall system. For instance, in a communication system, a baseband processor and a transceiver communicate with each other to exchange information for controlling the respective signal processing parts of the baseband processor and the transceiver. While Serial Peripheral Interfaces (SPIs) can be used, SPI can be extremely slow, and does not provide a protocol for allowing a complex set of control signals to be exchanged between the baseband processor and transceiver. The present disclosure describes a fast control interface which can support various modes of operation in allowing two devices to communicate with each other quickly and effectively.

Abstract: Devices exchange control signals with each other to ensure proper operation of an overall system. For instance, in a communication system, a baseband processor and a transceiver communicate with each other to exchange information for controlling the respective signal processing parts of the baseband processor and the transceiver. While Serial Peripheral Interfaces (SPIs) can be used, SPI can be extremely slow, and does not provide a protocol for allowing a complex set of control signals to be exchanged between the baseband processor and transceiver. The present disclosure describes a fast control interface which can support various modes of operation in allowing two devices to communicate with each other quickly and effectively.

Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.

Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.

Abstract: Devices exchange control signals with each other to ensure proper operation of an overall system. For instance, in a communication system, a baseband processor and a transceiver communicate with each other to exchange information for controlling the respective signal processing parts of the baseband processor and the transceiver. While Serial Peripheral Interfaces (SPIs) can be used, SPI can be extremely slow, and does not provide a protocol for allowing a complex set of control signals to be exchanged between the baseband processor and transceiver. The present disclosure describes a fast control interface which can support various modes of operation in allowing two devices to communicate with each other quickly and effectively.

Abstract: Devices exchange control signals with each other to ensure proper operation of an overall system. For instance, in a communication system, a baseband processor and a transceiver communicate with each other to exchange information for controlling the respective signal processing parts of the baseband processor and the transceiver. While Serial Peripheral Interfaces (SPIs) can be used, SPI can be extremely slow, and does not provide a protocol for allowing a complex set of control signals to be exchanged between the baseband processor and transceiver. The present disclosure describes a fast control interface which can support various modes of operation in allowing two devices to communicate with each other quickly and effectively.

Abstract: This disclosure relates to a distributed processing system for configuring multiple processing channels. The distributed processing system includes a main processor, such as an ARM processor, communicatively coupled to a plurality of co-processors, such as stream processors. The co-processors can execute instructions in parallel with each other and interrupt the ARM processor. Longer latency instructions can be executed by the main processor and lower latency instructions can be executed by the co-processors. There are several ways that a stream can be triggered in the distributed processing system. In an embodiment, the distributed processing system is a stream processor system that includes an ARM processor and stream processors configured to access different register sets. The stream processors can include a main stream processor and stream processors in respective transmit and receive channels. The stream processor system can be implemented in a radio system to configure the radio for operation.

Abstract: Apparatus and methods for transceiver calibration are provided. In certain configurations, a transceiver includes a transmit channel and an observation channel. The transmit channel includes a transmit mixer that up-converts a transmit signal by a first or transmit local oscillator frequency. The observation channel includes an observation mixer that down-converts an observed signal from the transmit channel by a second or observation local oscillator frequency that is offset from the first local oscillator frequency. By observing the transmit channel using a local oscillator frequency that is offset relative to the transmit channel's local oscillator frequency, the observation channel can observe transmit channel impairments substantially independently from observation channel impairments.

Abstract: Apparatus and methods for transceiver calibration are provided. In certain configurations, a transceiver includes a transmit channel and an observation channel. The transmit channel includes a transmit mixer that up-converts a transmit signal by a first or transmit local oscillator frequency. The observation channel includes an observation mixer that down-converts an observed signal from the transmit channel by a second or observation local oscillator frequency that is offset from the first local oscillator frequency. By observing the transmit channel using a local oscillator frequency that is offset relative to the transmit channel's local oscillator frequency, the observation channel can observe transmit channel impairments substantially independently from observation channel impairments.

Abstract: A circuit may include a detector, an approximator, a look-up table, a scaler, and an integrator. The detector may generate a first difference signal and a second different signal based on an input and an output. The approximator may generate, using a one's complement operation, an index based on approximated modulus values of the first difference signal and the second difference signal. The look-up table may select one of a plurality of scaling factors based upon the index. The scaler may adjust the first difference signal and the second difference signal based on the selected scaling factor. The integrator may generate the output based on the adjusted first difference signal and the adjusted second difference signal.

Abstract: A circuit may include a detector, an approximator, a look-up table, a scaler, and an integrator. The detector may generate a first difference signal and a second different signal based on an input and an output. The approximator may generate, using a one's complement operation, an index based on approximated modulus values of the first difference signal and the second difference signal. The look-up table may select one of a plurality of scaling factors based upon the index. The scaler may adjust the first difference signal and the second difference signal based on the selected scaling factor. The integrator may generate the output based on the adjusted first difference signal and the adjusted second difference signal.

Abstract: Apparatus and methods for estimating a direct current offset in an upconverter are disclosed. Samples of a first signal are received. Values of a compensation signal are retrieved. For example, the compensation signal can be a component in a modified baseband signal, wherein the modified baseband signal is upconverted, downconverted, and filtered to generate the first signal. An estimate of a first DC offset induced by an upconverter is generated based at least partly on at least two selected samples of the first signal and corresponding values of the compensation signal.