Abstract: A reconfigurable dataflow unit (RDU) includes an intra-RDU network, an array of configurable units connected by an array level network and function interfaces. The RDU also includes interface circuits coupled between the intra-RDU network and external interconnects. An interface circuit receives a packet from the external interconnect and extracts a target RDU identifier and compares the target RDU identifier to the value of the identity register. It also communicates over the intra-RDU network to a function interface based on information in the first packet in response to the target RDU identifier being equal to the identity register. The interface circuit retrieves another interface circuit identifier for the target RDU identifier from the pass-through table and, in response to the target RDU identifier not being equal to the identity register, sends the target RDU identifier and other information to the other interface circuit over the intra-RDU network.

Abstract: System and method for port arbitration in a switch network for dataflow computing systems, particularly in computer systems having a plurality reconfigurable processing units interconnected using switches. A switch network comprises a switch, a plurality of nodes coupled to the switch, and a Dynamic Equality of Service (DEoS) arbiter. The DEoS arbiter may perform operations to arbitrate among input ports of the switch to make a through-connection. Based on the port DEoS metrics, the arbiter selects an input port of the switch to make a through-connection to an output port of the switch. DEoS metrics may include DES counters, and/or quantization ranges of DEoS counters, associated with the source nodes.

Abstract: A reconfigurable data processor includes a bus system, an array of configurable units, and a configuration load controller connected to the bus system and coupled to a memory. The configuration load controller incorporates a first set of registers accessible from a host processor for storing addresses of a first configuration file, a second set of registers loaded by loading a configuration file for storing addresses of a second configuration file, and an address generation unit with working address registers. The processor is configured to load a first configuration file from the memory and initiate execution based on a request from runtime software. Additional configuration files are automatically loaded upon completion of a previous configuration file based on information stored in the previous configuration file.

Abstract: A coarse-grained reconfigurable (CGR) processor comprises a first network and a second network; a plurality of agents coupled to the first network; an array of CGR units coupled together by the second network; and a tile agent coupled between the first network and the second network. The tile agent comprises a plurality of links, a plurality of credit counters associated with respective agents of the plurality of agents, a plurality of credit-hog counters associated with respective links of the plurality of links, and an arbiter to manage access to the first network from the plurality of links based their associated credit-hog counters. Furthermore, a credit-hog counter of the plurality of credit-hog counters changes in response to processing a request for a transaction from its associated link.

Abstract: A reconfigurable processing unit is disclosed, comprising a first internal network and a second internal network with different protocols, an interface to an external network with a different protocol, a first configurable unit sending a request to access an external memory over the first internal network, a second configurable unit receiving the request on the first internal network, obtaining a memory address, determining an identifier for the target reconfigurable processing unit, and sending the request, identifier, and memory address over the second internal network, and a third configurable unit receiving the request, identifier, and memory address on the second internal network, determining a routable address on the external network based on the identifier, synthesizing a payload with the request, address, and identifier, and sending the payload to the routable address on the external network.

Abstract: A method comprises a Dynamic Equality of Service (DEoS) arbiter of a switch computing port DEoS metrics based on dynamic input activity of source nodes into input ports of the switch. Based on the port DEoS metrics, the arbiter selects an input port of the switch to make a through-connection to an output port of the switch. The port DEoS metrics can be based on node DEoS metrics including DEoS counters, and/or quantization ranges of DEoS counters, associated with the source nodes. A switching apparatus comprises a switch, a plurality of nodes coupled to the switch, and a DEoS arbiter. The switching apparatus can further comprise a first and second DEoS counter. The DEoS arbiter can perform operations of the method to arbitrate among input ports of the switch to make a through-connection.

Abstract: A coarse-grained reconfigurable architecture processor is disclosed, featuring an array of configurable units capable of executing an application with defined progress milestones. The processor includes a control bus connecting the configurable units and a hang detection circuit with a timer that resets upon receiving a control signal via the control bus. Upon reaching a progress milestone, a configurable unit sends a control signal to the hang detection circuit via the control bus. The hang detection circuit monitors the application's execution for hang conditions by detecting timer expiration, ensuring efficient and reliable processing of applications on the reconfigurable processor.

Abstract: A computing system is disclosed, comprising a host computer and multiple CGRPs (coarse-grained reconfigurable architecture processors) connected to the host computer through external communication links. Each CGRP includes an internal network, external interface circuits, memory interface circuits, arrays of configurable units, hang detection circuits, force-quit controllers, and a network recovery circuit with control registers. The host computer is programmed to configure and execute applications across the arrays of configurable units in both CGRPs. In case of a hang detection in one CGRP, the network recovery circuit initiates a force quit process and notifies the host computer. Additionally, the network recovery circuit compares application IDs and halts execution in the other CGRP if necessary. This system provides efficient failure tolerance and recovery mechanisms for parallel processing applications.

Abstract: Disclosed is a method for resetting configurable units in a reconfigurable processor with an array of configurable units and a force-quit controller on an integrated circuit substrate. The array includes multiple sub-arrays of configurable units. The method involves receiving a force-quit command at the force-quit controller and generating force-quit control signals to reset configurable units in a specific sub-array of the plurality of sub-arrays. The specific sub-array contains the force-quit controller. This method enhances the efficiency and reliability of reconfigurable processors by enabling targeted and controlled resets of configurable units within the reconfigurable processor architecture.

Abstract: A processor includes an internal network with separate packet-switching networks for request, response, data, and credit transmission. Each of the four networks includes switches interconnected by links. Interface circuits connect the internal network to communication links or electronic memory and communicate over the internal network. A network recovery circuit is also coupled to the internal network. Each switch has ports, buffers for input packets, routing circuitry to send packets to output ports based on destinations, and a watchdog timer to detect packet timeouts and notify the network recovery circuit of delays. The network recovery circuit responds to timeout messages by setting a network failure condition, ensuring efficient and reliable network operation.

Abstract: A Coarse-grained Reconfigurable Processor (CGRP) includes an internal network with request, response, and data networks operating concurrently as separate packet-switched networks. The CGRP includes external interface circuits coupled to an interface configurable unit in an array of configurable units through the internal network. The CGRP also includes a network health monitor circuit that is configured to detect network failure conditions by writing and then reading health monitor registers across the internal network.

Abstract: A processor has multiple memory interfaces and a memory interleaver controlling access to the memory interfaces. The memory interfaces may each couple with one or more memory devices. The number of memory devices coupled to the different memory interfaces may be unequal. The memory interleaver determines a memory region from a logical address, and a region relative address. It determines the interleave factor IF corresponding to the memory region. It performs an integer division to obtain a device line address, and a modulo operation to obtain an uncorrected channel address. The memory interleaver may add a region start address associated with the memory region to the device line address to obtain a physical line address. It may correct the uncorrected channel address, based on the memory region, to obtain a physical channel address. Some implementations use configuration memories to allow flexibility, other implementations are hardwired for a particular memory architecture.

Abstract: A computing system is disclosed, comprising a plurality of interconnected reconfigurable dataflow units (RDUs). Each RDU includes configurable units, internal networks, and external interfaces. The first configurable unit of the first RDU sends a request to access an external memory attached to the second RDU over its first internal network. The second configurable unit of the first RDU obtains a memory address for the request, determines an identifier for the second RDU, and sends the request, identifier, and memory address to the third configurable unit of the first RDU over its second internal network. The third configurable unit of the first RDU generates a routable address on the external network, synthesizes a payload, and sends it through an external network interface. The third configurable unit of the second RDU receives the payload, and the fourth configurable unit of the second RDU uses the address to access the external memory.

Abstract: A reconfigurable processor is disclosed, featuring an array of configurable units interconnected by a bus system. Each configurable unit includes a configuration data store structured as a shift register that includes individually addressable argument registers. Program load logic is responsible for receiving sub-files of configuration data through the bus system and sequentially shifting them into the configuration data store, including the argument registers. Argument load logic is designed to receive argument data via the bus system and directly load it into the argument registers without the need for shifting through the shift register.

Abstract: A computing system includes an array of configurable units made up of sub-arrays of configurable units. Each sub-array has a first number of configurable compute units and a second number of configurable memory units with a first spatial arrangement. Each configurable unit includes a configuration data store. The system also includes a statically configurable bus system coupled to the configurable units and a tag indicating a sub-array of configurable units having a defect. A defect-aware configuration controller sends configuration data to the configuration data stores to implement a data processing operation using the array of configurable units by generating static route control signals for the statically configurable bus system, based on the tag and without support of a host processor, to send a portion of the configuration data targeted to the sub-array having the defect to a configuration data store of an alternative sub-array of configurable units in the array.

Abstract: A dynamic peak power management system may prevent brownouts while improving performance and user experience compared to conventional techniques. A current threshold may be set below the maximum current capability (Imax) of a battery. If the current drawn from the battery exceeds the current threshold repeatedly, then system components may be throttled to decrease their peak power usage. If the current drawn from the battery stays below the current threshold for some time, then system components may be unthrottled to improve performance. This dynamic adaptable technique for managing peak power does not unnecessarily sacrifice performance by preemptively throttling system components to avoid the rare worst-case scenario where power spikes of system components perfectly align in time.

Abstract: A computing system includes a first network, a second network, multiple first agents connected to the first network, multiple second agents connected to the second network, and an interface circuit interconnecting the two networks. The interface circuit includes multiple request queues, a first arbiter for selecting requests from the second agents for transactions on the first network and entering them into the request queues, and credit counters associated with the first agents. A second arbiter selects requests from the oldest entry of each request queue based on the credit counters, sends transactions over the first network, and removes the selected requests from their respective queues. This system efficiently manages communication between the first and second networks, enhancing overall system performance.

Abstract: A method and system for unloading configuration data in a reconfigurable processor array comprises a bus system, and array of processor units connected to bus system, the processor units in the array including configuration data stores to store unit files comprising plurality of subfiles of configuration data particular to corresponding processor units. A configuration unload controller is connected to the bus system, including logic to execute an array configuration unload process, including distributing a command to plurality of the processor units in array to unload the unit files particular to corresponding processor units, the unit files each comprising plurality of ordered sub-files, receiving sub-files via bus system from the array of process units, and assembling an unload configuration file by arranging the received subfiles in memory according to the process unit of the unit file of which the subfile is a part, and order of the subfile in unit file.

Abstract: A method to access memory in a physical memory space includes receiving a logical line address (LLA) from a processor, converting the LLA to a physical line address (PLA) and a physical channel address (PCA), and accessing the memory using the PLA and PCA. The memory has multiple memory channels, and multiple memory regions. A memory device may occupy an intersection of a memory region and a memory channel. The conversion includes determining the memory region from the LLA, and determining a region relative address (RRA) from the LLA. The method determines an interleave factor (IF) from the region, and a device line address (DLA) and an uncorrected channel address (UCA) from the RRA and the IF. The method determines the PLA from the DLA and the memory region, and it determines the PCA from the UCA and the memory region.

Abstract: Argument registers in a reconfigurable processor are loaded from a runtime program running on a host processor. The runtime program stores a configuration file in a memory. A program load controller reads the configuration file from the memory and distributes it to configurable units in in the reconfigurable processor which sequentially shift it into a shift register of the configuration data store. The runtime program stores an argument load file in the memory and a fast argument load (FAL) controller reads the argument load file from memory and distributes (value, control) tuples to the configuration units in the reconfigurable processor. The configurable units process the tuples by writing the value directly into an argument register made up of a portion of the shift register in the configuration data store specified by the control of the tuple without shifting the value through the shift register.