Abstract: A method for processing machine information of a system, such as an integrated circuit design, to generate a display of a finite state machine diagram by determining a position for the states in the diagram and then showing representations of the transitions between states to create a symmetrical, compact and cyclic process view of the finite state machine. Levels are assigned to the states in a first direction. A rule based technique then is used to order the states in levels that ensure minimum crossings of transitions between consecutive levels as well as for transitions in a same level. Next, the specific position of each state in a second direction orthogonal to the first direction is computed, such that the positions take into account areas or “tracks” in which connection lines representing transitions between states will be rendered. The connection line representing transitions between states are then rendered in the diagram.