Abstract: A method and apparatus for testing an electronic device with multiple cores is provided. The method begins when at least one scan is input for scan configuring. A signal having a predetermined number of bits is then input to a decoder. The decoder then outputs at least one assigned test channel based on the output of the decoder. A test control block then switches at least one selected scan in channel to a test control block. A hard macro scan out of channels is then input to a channel maximization device which allocates or re-allocates the channels for testing. Testing proceeds once the channels are allocated. An apparatus includes a programmable scan configuration block for adjusting the number of scan out channels to maximize testing resources and a predetermined bit register in communication with the programmable scan configuration block.

Abstract: Embodiments contained in the disclosure provide a method of testing an electronic chip. The method comprises: scanning a test program into multiple clock registers; pulsing a clock to activate multiple asynchronous clock domain registers one at a time; staggering capture across and within the multiple asynchronous clock domains; shifting acquired data out of the multiple scan chains simultaneously; and then comparing the data scanned out with the test program data.