Abstract: Application validation is performed based at least in part on object level hierarchy data associated with the application. An application is executed on a physical or emulated host device, and assembly code is generated for the executing application. The assembly code is analyzed to identify objects associated with the application, and to identify relationships between the objects. Based on the object and relationship data, an object level hierarchy is generated for the application. Validation of the application may be performed by comparing an object level hierarchy for a current version of the application to a previously generated hierarchy for a previous version of the application to identify differences between to the two hierarchies.

Abstract: An electronic device in a low power mode, for example an eBook reader device, may use a fast awake module to quickly update a display. The electronic device may receive an interrupt, begin to awaken, present a cached pre-rendered image on the display, and may resume the low power mode or pre-render additional images to refill the cache before resuming the low power mode.

Abstract: Some implementations provide power management techniques for an electronic device that receives power through a USB port. The device may receive power from various different power sources such as a PC, USB hub, and various types of power adapters. To identify a type of power adapter connected to the USB port, the device's USB device controller may be reconfigured to operate in a host mode. A pull-up or pull-down may be placed on one of the D+ or D? lines of the USB port for determining whether the lines are shorted or floating. When the lines are shorted, the power source may be identified as a first type of power adapter that provides a known level of current. When the lines are not shorted, the values of the lines may be compared with known values for one or more pull-ups or pull-downs to attempt to identify other known power adapters.

Abstract: A device controller, such as a universal serial bus (“USB”) device controller, that is unattached to an external device is placed into a low power mode. During low power mode, interface components of the device controller are gated or placed into a reduced power state. For example, components such as a USB gadget PHY, which manages physical layer communication, USB direct memory access clock, secondary clocks, and so forth may be gated. Upon receiving a connection event indicating attachment of a device to the USB, the device controller resumes normal power operation. This device controller low power mode may work in conjunction with state retention modes or other low power modes affecting other components within an electronic device.

Abstract: External jolts, such as those occurring during shipment, may inadvertently activate an electronic device. Such inadvertent activations may result in the electronic device entering an active mode during shipment, draining battery power. This document describes a power cut off mode that prevents inadvertent device activations and minimizes current consumption during shipment or storage of a device. This conserves battery power for operational use by the user.

Abstract: A deep idle mode for electronic devices is described, which provides significant power savings while allowing significantly shorter resumption times than experienced with a suspend mode. During deep idle mode, a root clock such as the microcontroller unit phase-locked loop (MPLL) is scaled or gated entirely and other clocks such as the processor, memory, and general purpose timer clocks may be scaled. To maintain functionality while these clocks are scaled or gated, an external clock source couples to the processor, memory, and a general purpose timer.

Abstract: An interrupt reducing device driver module reduces the rate at which interrupts from a peripheral burden a processor. The interrupt reducing device driver determines when data is associated with the interrupt. When data is present, such as when indicated by an interrupt status register, further interrupts are masked and a buffer associated with the peripheral is read-out. This read-out continues while data is present in the buffer. Once no further data is present, the data interrupts are unmasked. Reduction in the rate of interrupts prevents resource starvation and improves overall system response. Additionally, the processor and associated components are able to enter and remain in low power modes, improving battery life.

Abstract: A quiescent state retention mode (QSRM) permits minimal power consumption and dissipation by an electronic device while idle without producing adverse latencies to users or causing system instability. Upon a call to enter the QSRM, processes may be frozen, clocks may be gated, switching regulators may be placed in low power mode, SDRAM may be placed into self-refresh mode, caches may be flushed, IRQs may be disabled, and the system waits for interrupt to wakeup. In the QSRM, powered components include the switching regulator configured to provide power to the processor is maintained in a low power mode while the SDRAM is placed in self-refresh.

Abstract: An idle universal serial bus (“USB”) is placed into a low power mode. During low power mode, peripherals attached to the USB bus may also enter a low power mode. While in this low power mode, USB attached peripherals may retain some functionality. For example, a USB attached modem may remain connected, allowing rapid resumption of communications upon awakening.

Abstract: Microprocessor-based devices may experience crashes due to failures in software, hardware, or a combination thereof. Details about a crash may provide valuable information for determining cause of the crash. Devices may save crash information in volatile memory, place the volatile memory into a self-refresh mode, power cycle the remainder of the device, reboot, and retrieve the crash information. Other information to be persisted across a power cycle may also be saved to volatile memory in this fashion as well.

Abstract: Transfer of data blocks between a host and a multi-media card (“MMC”) are performed in a pre-defined mode. In pre-defined mode, the host sets a pre-determined number of blocks, a “multiblock,” to be transferred. Use of pre-defined mode results in faster transfers than those performed using an open-ended mode incorporating a stop command. Furthermore, corruption errors resulting from delays in providing the stop command which may occur in an open-ended mode are avoided. Pre-defined multiblock transfers are supported by existing operating systems through trapping open-ended mode transfers in the MMC stack, leaving existing device drivers unaffected.

Abstract: A quiescent state retention mode (QSRM) permits minimal power consumption and dissipation by an electronic device while idle without producing adverse latencies to users or causing system instability. Upon a call to enter the QSRM, processes may be frozen, clocks may be gated, switching regulators may be placed in low power mode, SDRAM may be placed into self-refresh mode, caches may be flushed, IRQs may be disabled, and the system waits for interrupt to wakeup. In the QSRM, powered components include the switching regulator configured to provide power to the processor is maintained in a low power mode while the SDRAM is placed in self-refresh.