Abstract: A balanced mixer circuit (300, 400, 500, 600, 700 and 800) in a baseband receiver (202) includes an oscillator circuit (212), a mixer (214 and 215), a digital-to-analog converter (258 and 259) and a digital signal processor (250). The mixer includes CMOS devices (301, 302, 303 and 304). In response to differential outputs from the mixer, the digital signal processor controls the digital-to-analog converter to output bias voltages for the gate of at least one of the CMOS devices of the mixer to compensate for imbalance in the differential output of the mixer that may be caused by mismatch among two or more CMOS devices of the mixer or caused by other reasons, in order to increase second order intercept point of the mixer.

Abstract: A method and apparatus are provided for providing improved radio frequency (RF) receiver signal correction. For RF receiver circuitry (106) having receive path and a warmup period associated therewith and including at least one analog baseband gain control stage (218) having a gain associated therewith, the method includes the step of performing a DC correction calculation operation during the warmup period to derive a DC correction value having a first component and a second component for each of the at least one gain control stage (218). The DC correction calculation step includes the steps of performing a first closed loop correction (460) of a baseband path to derive the first component of the DC correction value and performing a second closed loop correction (462) of the receive path as a function of the (218) gain during the warmup period to derive the second component of the DC correction value.

Abstract: Methods and corresponding systems for receiving a radio frequency signal include a receiver capable of switching operating modes and operable to receive the radio frequency signal in any of the operating modes. A metric monitor is coupled to the receiver and operable to provide a metric. A controller is responsive to the metric and operable to switch the receiver between the operating modes. The operating modes can include a zero intermediate frequency (ZIF) mode and a very low intermediate frequency (VLIF) mode. The metric can include a received signal strength indicator (RSSI) and an adjacent channel indicator. The receiver can be configured to operate in the ZIF mode in response to the RSSI value satisfying a threshold and configured to operate in the VLIF mode in response to the RSSI value failing to satisfy the threshold.

Abstract: A balanced mixer circuit (300, 400, 500, 600, 700 and 800) in a baseband receiver (202) includes an oscillator circuit (212), a mixer (214 and 215), a digital-to-analog converter (258 and 259) and a digital signal processor (250). The mixer includes CMOS devices (301, 302, 303 and 304). In response to differential outputs from the mixer, the digital signal processor controls the digital-to-analog converter to output bias voltages for the gate of at least one of the CMOS devices of the mixer to compensate for imbalance in the differential output of the mixer that may be caused by mismatch among two or more CMOS devices of the mixer or caused by other reasons, in order to increase second order intercept point of the mixer.

Abstract: A high performance radio frequency receiver includes an isolated transconductance amplifier with large binary and stepped gain control range, controlled impedance, and enhanced blocker immunity, for amplifying and converting a radio frequency signal to multiple electrically isolated currents; a pulse generator for generating in-phase and quadrature pulses; a crossover correction circuit and pulse shaper for controlling a crossover threshold of the pulses and interaction between in-phase and quadrature mixers; and a double balanced mixer for combining the RF signal with the pulses to generate an intermediate frequency or baseband zero intermediate frequency current-mode signal. The intermediate frequency signal and second order harmonics may be filtered with a high frequency low pass filter and a current injected complex direct-coupled filter. IIP2 calibration of the in-phase and quadrature channels may be optimized using the isolated transconductance amplifier.

Abstract: A high performance radio frequency receiver includes a low noise amplifier with large binary and stepped gain control range, controlled impedance, and enhanced blocker immunity, for amplifying and converting a radio frequency signal to a current; a pulse generator for generating in-phase and quadrature pulses; a crossover correction circuit and pulse shaper for controlling a crossover threshold of the pulses and interaction between in-phase and quadrature mixers; and a double balanced mixer for combining the RF signal with the pulses to generate an intermediate frequency or baseband zero intermediate frequency current-mode signal. The in-phase and quadrature pulses have a duty cycle of 20-35%. The intermediate frequency signal and second order harmonics may be filtered with a high frequency low pass filter and a current injected complex direct-coupled filter.

Abstract: An IP2 tuning circuit (404, 1004, 1104 and 1404) for tuning the IP2 of a mixer (414 and 415) to minimize second order intermodulation distortion (IMD2) in a receiver (402, 1002, 1102 and 1402) of a transceiver (401, 1001, 1101 and 1401). An operating characteristic of the mixer related to IMD2 is changeable by changing a value of a setting of the mixer. Two tones outside a bandpass of the receiver are injected into the mixer and a calibration tone within the bandpass is produced as a result of IMD2. Alternatively, a DSSS signal is injected into the mixer and the calibration tone is produced at a chip rate of the DSSS signal. The power of the calibration tone is measured at a plurality of values of the settings. Alternatively, a four-level PN DSSS signal of known content is injected into the mixer, and a two-level PN DSSS signal of known content produced therefrom is correlated with a two-level PN DSSS signal of known content produced by a squaring circuit (1468).