Abstract: Methods that may be performed by a universal flash storage (UFS) device of a computing device for configuring flash memory cells. Various embodiments may include setting a number of degraded triple-level cells (TLCs) attribute, and configuring at least one degraded TLC as at least one single-level cell (SLC) based on the number of degraded TLCs attribute, the at least one degraded TLC being not functional as a TLC and functional as an SLC. Some embodiments may include identifying the at least one degraded TLC based on at least one degradation attribute associated with the at least one degraded TLC, the at least one degradation attribute configured to indicate that the at least one degraded TLC is not functional as a TLC, and identifying an amount of degraded TLCs that are not functional as a TLC.

Abstract: An example electronic computing device can be programmed to: receive a status and a date for each of a plurality of loan components associated with a loan transaction, the loan transaction being purchase or refinance of a loan for a property; use an operating service level associated with each of the plurality of loan components to calculate a projected completion date for each of the plurality of loan components; and project a closing date based upon a longest of the projected completion date. The electronic computing device can calculate the operating service levels using artificial intelligence.

Abstract: The innovation disclosed and claimed herein, in one aspect thereof, comprises systems, methods and computer program products that enable transactions requested by a user using a trade asset card. The innovation enables the transactions to be completed in real time or near real time per pre-determined rules and settings, or audited changes to rules and settings, while staying perpetually invested in the user's investment portfolio.

Abstract: The present provides a simple, convenient and time-efficient process for the preparation of propofol. Particularly, the present invention provides an improved process for the preparation of propofol using a heterocyclic base for the decarboxylation reaction. The present invention provides a time-efficient process for the preparation of propofol with high yield and purity.

Abstract: The concept involves efficiently using machine learning to quickly identify possible fraudulent applications in small business loan and credit applications by automatically flagging applications that meet certain criteria. In one preferred implementation, the tool compares a business description to a selected NAICS code in a loan application to assess the potential for fraud. Specifically, an algorithm can match the leftmost two digits of the selected code with the description of the category from an applicant. An engine calculates a probability of a fraud score based on the matching attached to the application. Because the tool detects fraud proactively rather than reactively, it substantially reduces computational costs and resources and reduces the biases associated with highly intensive manual work.

Abstract: Various examples are directed to systems and methods for visualizing computerized model decisions. A model system may access result data that comprises event results for a plurality of events and event feature data describing sets of event features. A first event result for a first event of the plurality of events is generated using the computerized model and a first set of event features from the event feature data. The model system may access importance score data comprising importance scores for at least a portion of the first set of event features, wherein a first event feature is assigned a first importance score and a second event feature is assigned a second importance score indicating a greater importance than the first importance score. The model system may also generate a user interface for display to a human user. The user interface may comprise a background area; a first visual indicator positioned on the background area and corresponding to the first event feature.

Abstract: Described herein is an illuminating device with reflector. Said device includes a heat sink insert moulded cylindrical plastic housing, and a circular metal core printed circuit board, MCPCB, mounted on a circular slot provided on a top inner end of the housing, the circular MCPCB having light emitting diodes (LEDs), wherein LEDs mounted in a circular manner near peripheral region of a top surface of the MCPCB and having electronic components mounted in a central region of the top surface of the MCPCB. Further said device includes a cylindrical reflector fixed on the top surface of the MCPCB with its cylindrical wall lying between the LEDs and the electronic components; and a diffuser connecting a top surface of the cylindrical reflector with the top inner end of the housing, wherein lower end of said plastic housing connected with a holder.

Abstract: The innovation disclosed and claimed herein, in one aspect thereof, comprises systems, methods and computer program products that enable transactions requested by a user using a trade asset card. The innovation enables the transactions to be completed in real time or near real time per pre-determined rules and settings, or audited changes to rules and settings, while staying perpetually invested in the user's investment portfolio.

Abstract: A machine learning model predicts the hardness of unsolved properties. For example, the machine learning model may predict the relative hardness of pairs of properties—i.e., which property in the pair is harder to solve. These hardness predictions may then be used to formulate a priority order for a formal verification process to attempt to solve the unsolved properties. As the formal verification process progresses, it generates results. For example, certain properties may be solved. These results are used to update a training set, which is used to further train the machine learning model. The machine learning model is trained at runtime with incremental fine-tuning as the formal verification process progresses.

Abstract: Systems and methods create and modify augmented deal structure using specialized components working together in a technical system by aggregating and transforming inputs. Big Data issues are controlled and restriction rules along with specialized components work together to synthesize an augmented deal structure. This augmented structure is presented through a graphical user interface configured to provide at least one of an interactive analysis (providing sensitivity analytics) and a batch processing capability.

Abstract: Various examples are directed to systems and methods for visualizing computerized model decisions. A model system may access result data that comprises event results for a plurality of events and event feature data describing sets of event features. A first event result for a first event of the plurality of events is generated using the computerized model and a first set of event features from the event feature data. The model system may access importance score data comprising importance scores for at least a portion of the first set of event features, wherein a first event feature is assigned a first importance score and a second event feature is assigned a second importance score indicating a greater importance than the first importance score. The model system may also generate a user interface for display to a human user. The user interface may comprise a background area; a first visual indicator positioned on the background area and corresponding to the first event feature.

Abstract: A method or apparatus comprising a verification system using a processor to utilize a first set of verification engines to solve easy properties of an integrated circuit design, such as RTL, running a machine-learning algorithm for a hardness ranking analysis on a plurality of properties based on data from the first set of verification engines, and ranking the plurality of properties by a hardness of verification. The method or apparatus further to order the plurality of properties based on the hardness of verification.

Abstract: A formal verification tool that verifies multiple sequentially-generated versions of a core circuit design by obtaining search path information from the formal verification solver for each property that is proven or disproven during a first formal verification session involving an earlier-generated circuit design version, and utilizing the search path information to perform search-path verification processes during a subsequent formal verification session to quickly verify the proven/disproven properties in a later-generated circuit design version. Each property's search path information includes counterexample traces or proof artifacts identifying the search operations utilized to achieve a corresponding counterexample or proof object that proves/disproves the property. Search-path verification involves applying the stored search path information to the later-generated circuit design version, and determining if the same counterexample or proof object is achieved.

Abstract: A method, system or computer usable program product for model checking a first circuit model including receiving a request from a user for a model check of the first circuit model; responsive to receiving the user request, simulating the first circuit model to generate simulation results; hashing the first circuit model simulation results to generate a hash index; comparing the hash index to a database of prior hash indices generated from hashed simulation results of prior circuit models to determine whether the first circuit model hash index matches a prior hash index of any of the prior circuit models to identify a matching prior circuit model; upon a positive match, determining whether the first circuit model is equivalent to the matching prior circuit model; and upon a positive determination of equivalence, providing prior test results of the matching prior circuit model to the user.

Abstract: A method or apparatus comprising a verification system using a processor to utilize a first set of verification engines to solve easy properties of an integrated circuit design, such as RTL, and running a machine-learning algorithm for hardness ranking analysis on a plurality of properties based on data from the first set of verification engines, and ranking the plurality of properties by a hardness of verification. The method of apparatus further to order the plurality of properties based on the hardness of verification.

Abstract: A method, system or computer usable program product for model checking a first circuit model including determining whether the first circuit model is functionally equivalent to one of a set of prior circuit models stored in persistent memory, and in response to determining functional equivalence, utilizing a processor to provide test results for the functionally equivalent prior circuit model.

Abstract: A method, system or computer usable program product for model checking a first circuit model including receiving a request from a user for a model check of the first circuit model; responsive to receiving the user request, simulating the first circuit model to generate simulation results; hashing the first circuit model simulation results to generate a hash index; comparing the hash index to a database of prior hash indices generated from hashed simulation results of prior circuit models to determine whether the first circuit model hash index matches a prior hash index of any of the prior circuit models to identify a matching prior circuit model; upon a positive match, determining whether the first circuit model is equivalent to the matching prior circuit model; and upon a positive determination of equivalence, providing prior test results of the matching prior circuit model to the user.

Abstract: A method, system or computer usable program product for model checking a first circuit model including determining whether the first circuit model is functionally equivalent to one of a set of prior circuit models stored in persistent memory, and in response to determining functional equivalence, utilizing a processor to provide test results for the functionally equivalent prior circuit model.

Abstract: A method and system for generating design constraints for an electronic circuit design is disclosed. The method and system include reading a design description and an existing design constraint file, configuring design constraint integration rules, writing a new design constraint file, evaluating results of the new design constraint file, and replacing existing design constraint file with the new design constraint file.

Abstract: A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.