Patents by Inventor Manish Pandey

Manish Pandey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11947919
    Abstract: The present invention relates to a method for facilitating a human-machine conversation for responding to a user query received from a user. The method includes determining at least one of a category and a context of the user query and implementing a first model and a second model for responding to the user query. The second model is triggered when the first model is unable to respond to the user query. The method further includes configuring one or more crawlers for accessing corresponding one or more databases of a plurality of databases for retrieving the relevant information and generating a second model. The method also includes enabling the second model to present the relevant information to the user based on the second model score. The second model updates the first model with the relevant information and its corresponding second model score.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: April 2, 2024
    Assignee: Zensar Technologies Limited
    Inventors: Sridhar Gadi, Manish Kumar, Pavan Jakati, Neeraj Pandey
  • Patent number: 11922505
    Abstract: The innovation disclosed and claimed herein, in one aspect thereof, comprises systems, methods and computer program products that enable transactions requested by a user using a trade asset card. The innovation enables the transactions to be completed in real time or near real time per pre-determined rules and settings, or audited changes to rules and settings, while staying perpetually invested in the user's investment portfolio.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: March 5, 2024
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Rameshchandra Bhaskar Ketharaju, Manish Pandey, Prabal Nandi, Shanmukeswara Rao Donkada
  • Publication number: 20230174444
    Abstract: The present provides a simple, convenient and time-efficient process for the preparation of propofol. Particularly, the present invention provides an improved process for the preparation of propofol using a heterocyclic base for the decarboxylation reaction. The present invention provides a time-efficient process for the preparation of propofol with high yield and purity.
    Type: Application
    Filed: March 25, 2021
    Publication date: June 8, 2023
    Applicant: FRESENIUS KABI ONCOLOGY LTD.
    Inventors: Ashwani Kumar SHARMA, Manish PANDEY, Abhishek GIRI, Sarbjot Singh SOKHI, Govind SINGH, Saswata LAHIRI, Walter CABRI
  • Patent number: 11605126
    Abstract: The concept involves efficiently using machine learning to quickly identify possible fraudulent applications in small business loan and credit applications by automatically flagging applications that meet certain criteria. In one preferred implementation, the tool compares a business description to a selected NAICS code in a loan application to assess the potential for fraud. Specifically, an algorithm can match the leftmost two digits of the selected code with the description of the category from an applicant. An engine calculates a probability of a fraud score based on the matching attached to the application. Because the tool detects fraud proactively rather than reactively, it substantially reduces computational costs and resources and reduces the biases associated with highly intensive manual work.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: March 14, 2023
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Jie Chen, Carmel Nadav, Manish Pandey
  • Patent number: 11599579
    Abstract: Various examples are directed to systems and methods for visualizing computerized model decisions. A model system may access result data that comprises event results for a plurality of events and event feature data describing sets of event features. A first event result for a first event of the plurality of events is generated using the computerized model and a first set of event features from the event feature data. The model system may access importance score data comprising importance scores for at least a portion of the first set of event features, wherein a first event feature is assigned a first importance score and a second event feature is assigned a second importance score indicating a greater importance than the first importance score. The model system may also generate a user interface for display to a human user. The user interface may comprise a background area; a first visual indicator positioned on the background area and corresponding to the first event feature.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: March 7, 2023
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Carmel Nadav, Manish Pandey, Connor Patrick Jennings, Mahima Rawat
  • Patent number: 11512844
    Abstract: Described herein is an illuminating device with reflector. Said device includes a heat sink insert moulded cylindrical plastic housing, and a circular metal core printed circuit board, MCPCB, mounted on a circular slot provided on a top inner end of the housing, the circular MCPCB having light emitting diodes (LEDs), wherein LEDs mounted in a circular manner near peripheral region of a top surface of the MCPCB and having electronic components mounted in a central region of the top surface of the MCPCB. Further said device includes a cylindrical reflector fixed on the top surface of the MCPCB with its cylindrical wall lying between the LEDs and the electronic components; and a diffuser connecting a top surface of the cylindrical reflector with the top inner end of the housing, wherein lower end of said plastic housing connected with a holder.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: November 29, 2022
    Inventors: Mohit K. Mittal, Manish Pandey, R. K. Sharma
  • Patent number: 11508009
    Abstract: The innovation disclosed and claimed herein, in one aspect thereof, comprises systems, methods and computer program products that enable transactions requested by a user using a trade asset card. The innovation enables the transactions to be completed in real time or near real time per pre-determined rules and settings, or audited changes to rules and settings, while staying perpetually invested in the user's investment portfolio.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: November 22, 2022
    Assignee: WELLS FARGO BANK, N.A.
    Inventors: Rameshchandra Bhaskar Ketharaju, Manish Pandey, Prabal Nandi, Shanmukeswara Rao Donkada
  • Patent number: 11501048
    Abstract: A machine learning model predicts the hardness of unsolved properties. For example, the machine learning model may predict the relative hardness of pairs of properties—i.e., which property in the pair is harder to solve. These hardness predictions may then be used to formulate a priority order for a formal verification process to attempt to solve the unsolved properties. As the formal verification process progresses, it generates results. For example, certain properties may be solved. These results are used to update a training set, which is used to further train the machine learning model. The machine learning model is trained at runtime with incremental fine-tuning as the formal verification process progresses.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: November 15, 2022
    Assignee: Synopsys, Inc.
    Inventors: Arunava Saha, Chuan Jiang, Manish Pandey
  • Publication number: 20220277394
    Abstract: Systems and methods create and modify augmented deal structure using specialized components working together in a technical system by aggregating and transforming inputs. Big Data issues are controlled and restriction rules along with specialized components work together to synthesize an augmented deal structure. This augmented structure is presented through a graphical user interface configured to provide at least one of an interactive analysis (providing sensitivity analytics) and a batch processing capability.
    Type: Application
    Filed: December 14, 2017
    Publication date: September 1, 2022
    Inventors: Carmel Nadav, Manish Pandey, Zachary Washam
  • Patent number: 11074302
    Abstract: Various examples are directed to systems and methods for visualizing computerized model decisions. A model system may access result data that comprises event results for a plurality of events and event feature data describing sets of event features. A first event result for a first event of the plurality of events is generated using the computerized model and a first set of event features from the event feature data. The model system may access importance score data comprising importance scores for at least a portion of the first set of event features, wherein a first event feature is assigned a first importance score and a second event feature is assigned a second importance score indicating a greater importance than the first importance score. The model system may also generate a user interface for display to a human user. The user interface may comprise a background area; a first visual indicator positioned on the background area and corresponding to the first event feature.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 27, 2021
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Carmel Nadav, Manish Pandey, Connor Patrick Jennings, Mahima Rawat
  • Patent number: 10521536
    Abstract: A method or apparatus comprising a verification system using a processor to utilize a first set of verification engines to solve easy properties of an integrated circuit design, such as RTL, running a machine-learning algorithm for a hardness ranking analysis on a plurality of properties based on data from the first set of verification engines, and ranking the plurality of properties by a hardness of verification. The method or apparatus further to order the plurality of properties based on the hardness of verification.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: December 31, 2019
    Assignee: Synopsys, Inc.
    Inventors: Jinqing Yu, Manish Pandey, Ming-Ying Chung, Arunava Saha
  • Patent number: 10503853
    Abstract: A formal verification tool that verifies multiple sequentially-generated versions of a core circuit design by obtaining search path information from the formal verification solver for each property that is proven or disproven during a first formal verification session involving an earlier-generated circuit design version, and utilizing the search path information to perform search-path verification processes during a subsequent formal verification session to quickly verify the proven/disproven properties in a later-generated circuit design version. Each property's search path information includes counterexample traces or proof artifacts identifying the search operations utilized to achieve a corresponding counterexample or proof object that proves/disproves the property. Search-path verification involves applying the stored search path information to the later-generated circuit design version, and determining if the same counterexample or proof object is achieved.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 10, 2019
    Assignee: Synopsys, Inc.
    Inventors: Arunava Saha, Himanshu Jain, Manish Pandey, Ashvin Dsouza, Per Mattias Bjesse
  • Patent number: 10140403
    Abstract: A method, system or computer usable program product for model checking a first circuit model including receiving a request from a user for a model check of the first circuit model; responsive to receiving the user request, simulating the first circuit model to generate simulation results; hashing the first circuit model simulation results to generate a hash index; comparing the hash index to a database of prior hash indices generated from hashed simulation results of prior circuit models to determine whether the first circuit model hash index matches a prior hash index of any of the prior circuit models to identify a matching prior circuit model; upon a positive match, determining whether the first circuit model is equivalent to the matching prior circuit model; and upon a positive determination of equivalence, providing prior test results of the matching prior circuit model to the user.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: November 27, 2018
    Assignee: SYNOPSYS INC.
    Inventors: Jinqing Yu, Manish Pandey
  • Publication number: 20180144071
    Abstract: A method or apparatus comprising a verification system using a processor to utilize a first set of verification engines to solve easy properties of an integrated circuit design, such as RTL, and running a machine-learning algorithm for hardness ranking analysis on a plurality of properties based on data from the first set of verification engines, and ranking the plurality of properties by a hardness of verification. The method of apparatus further to order the plurality of properties based on the hardness of verification.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 24, 2018
    Inventors: Jinqing Yu, Manish Pandey, Ming-Ying Chung, Arunava Saha
  • Patent number: 9430595
    Abstract: A method, system or computer usable program product for model checking a first circuit model including determining whether the first circuit model is functionally equivalent to one of a set of prior circuit models stored in persistent memory, and in response to determining functional equivalence, utilizing a processor to provide test results for the functionally equivalent prior circuit model.
    Type: Grant
    Filed: December 1, 2012
    Date of Patent: August 30, 2016
    Assignee: Synopsys, Inc.
    Inventors: Manish Pandey, Jinqing Yu
  • Publication number: 20160125111
    Abstract: A method, system or computer usable program product for model checking a first circuit model including receiving a request from a user for a model check of the first circuit model; responsive to receiving the user request, simulating the first circuit model to generate simulation results; hashing the first circuit model simulation results to generate a hash index; comparing the hash index to a database of prior hash indices generated from hashed simulation results of prior circuit models to determine whether the first circuit model hash index matches a prior hash index of any of the prior circuit models to identify a matching prior circuit model; upon a positive match, determining whether the first circuit model is equivalent to the matching prior circuit model; and upon a positive determination of equivalence, providing prior test results of the matching prior circuit model to the user.
    Type: Application
    Filed: January 12, 2016
    Publication date: May 5, 2016
    Inventors: Jinqing Yu, Manish Pandey
  • Publication number: 20140157216
    Abstract: A method, system or computer usable program product for model checking a first circuit model including determining whether the first circuit model is functionally equivalent to one of a set of prior circuit models stored in persistent memory, and in response to determining functional equivalence, utilizing a processor to provide test results for the functionally equivalent prior circuit model.
    Type: Application
    Filed: December 1, 2012
    Publication date: June 5, 2014
    Applicant: SYNOPSYS INC.
    Inventors: Manish Pandey, Jinqing Yu
  • Patent number: 8627249
    Abstract: A method and system for generating design constraints for an electronic circuit design is disclosed. The method and system include reading a design description and an existing design constraint file, configuring design constraint integration rules, writing a new design constraint file, evaluating results of the new design constraint file, and replacing existing design constraint file with the new design constraint file.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: January 7, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Manish Pandey, Marcalo Glusman, Angela Krstic, Yee-Wing Hsieh, Andy Lin
  • Patent number: 8516422
    Abstract: A method for implementing a single file format for power-related information for an IC comprising: providing a circuit design in at least one design file in a non-transitory computer readable storage device; providing power-related design information in a file in the computer readable storage device that is separate from the at least one design file and that specifies multiple power domains within the circuit design, each power domain including one or more design object instances from within the circuit design and that specifies multiple power modes each power mode corresponding to a different combination of on/off states of the multiple specified power domains and that specifies isolation behavior relative to respective power domains; and using a computer to add power control circuitry to the circuit design that implements the power domains and power modes and isolation behavior specified in the power specification information.
    Type: Grant
    Filed: June 14, 2010
    Date of Patent: August 20, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Qi Wang, Ankur Gupta, Pinhong Chen, Christina Chu, Manish Pandey, Huan-Chih Tsai, Sandeep Bhatia, Yonghao Chen, Steven Sharp, Vivek Chickermane, Patrick Gallagher
  • Patent number: RE44479
    Abstract: A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: September 3, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Qi Wang, Ankur Gupta, Pinhong Chen, Christina Chu, Manish Pandey, Huan-Chih Tsai, Sandeep Bhatia, Yonghoa Chen, Steven Sharp, Vivek Chickermane, Patrick Gallagher, Mitchell W. Hines