Abstract: A battery protector includes analog frontend circuitry coupled to a hibernate mode input terminal that is one of configured to couple to a high voltage connector terminal when the system is connected to an external load or charger to define an active mode and configured to float when the system is disconnected from the external load or charger to define a hibernate mode. The analog frontend circuitry is configured to provide a signal at an output thereof to distinguish, in the absence of an external ground connection, between connected and floating conditions for the hibernate mode input terminal. Digital logic is coupled with the output of the analog frontend circuitry, the digital logic providing a digital signal to control whether the battery protector is operating in the active mode or the hibernate mode based on the signal at the output of the analog frontend circuitry.

Abstract: A cell balancing system includes sensing circuitry configured to sense a cell voltage of each of a plurality of cells of a battery. Cell balancing circuitry is configured to balance each of the plurality of cells in response to a respective cell balancing command for each of the plurality of cells. A comparison circuit configured to compare the sensed cell voltages for each of the plurality of cells to an adaptive threshold voltage. The comparison circuit generates a respective cell state for each of the plurality of cells to indicate a state of the respective cell voltage for each of the plurality of cells relative to the adaptive threshold voltage. A controller is configured to set the respective cell balancing command for each of the plurality of cells and to adjust the adaptive threshold voltage based on an evaluation of the cell states for the plurality of cells.

Abstract: A battery system includes a position detector configured to detect whether a first battery protector is coupled to a second power rail and positioned at a bottom of a stack. A cell balancing input (CBI) is coupled to receive a CBI signal to enable or disable cell balancing of the first battery protector. A cell balancing output (CBO) enables cell balancing of a second protector in the stack.

Abstract: A cell balancing system includes sensing circuitry configured to sense a cell voltage of each of a plurality of cells of a battery. Cell balancing circuitry is configured to balance each of the plurality of cells in response to a respective cell balancing command for each of the plurality of cells. A comparison circuit configured to compare the sensed cell voltages for each of the plurality of cells to an adaptive threshold voltage. The comparison circuit generates a respective cell state for each of the plurality of cells to indicate a state of the respective cell voltage for each of the plurality of cells relative to the adaptive threshold voltage. A controller is configured to set the respective cell balancing command for each of the plurality of cells and to adjust the adaptive threshold voltage based on an evaluation of the cell states for the plurality of cells.

Abstract: A cell balancing system includes sensing circuitry configured to sense a cell voltage of each of a plurality of cells of a battery. Cell balancing circuitry is configured to balance each of the plurality of cells in response to a respective cell balancing command for each of the plurality of cells. A comparison circuit configured to compare the sensed cell voltages for each of the plurality of cells to an adaptive threshold voltage. The comparison circuit generates a respective cell state for each of the plurality of cells to indicate a state of the respective cell voltage for each of the plurality of cells relative to the adaptive threshold voltage. A controller is configured to set the respective cell balancing command for each of the plurality of cells and to adjust the adaptive threshold voltage based on an evaluation of the cell states for the plurality of cells.

Abstract: A cell balancing system includes sensing circuitry configured to sense a cell voltage of each of a plurality of cells of a battery. Cell balancing circuitry is configured to balance each of the plurality of cells in response to a respective cell balancing command for each of the plurality of cells. A comparison circuit configured to compare the sensed cell voltages for each of the plurality of cells to an adaptive threshold voltage. The comparison circuit generates a respective cell state for each of the plurality of cells to indicate a state of the respective cell voltage for each of the plurality of cells relative to the adaptive threshold voltage. A controller is configured to set the respective cell balancing command for each of the plurality of cells and to adjust the adaptive threshold voltage based on an evaluation of the cell states for the plurality of cells.

Abstract: A battery system includes a position detector configured to detect whether a first battery protector is coupled to a second power rail and positioned at a bottom of a stack. A cell balancing input (CBI) is coupled to receive a CBI signal to enable or disable cell balancing of the first battery protector. A cell balancing output (CBO) enables cell balancing of a second protector in the stack.

Abstract: A battery protector includes analog frontend circuitry coupled to a hibernate mode input terminal that is one of configured to couple to a high voltage connector terminal when the system is connected to an external load or charger to define an active mode and configured to float when the system is disconnected from the external load or charger to define a hibernate mode. The analog frontend circuitry is configured to provide a signal at an output thereof to distinguish, in the absence of an external ground connection, between connected and floating conditions for the hibernate mode input terminal. Digital logic is coupled with the output of the analog frontend circuitry, the digital logic providing a digital signal to control whether the battery protector is operating in the active mode or the hibernate mode based on the signal at the output of the analog frontend circuitry.

Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic is configured to selectively couple a signal received on a second external pin of the IC either directly or via the buffer to the first external pin of the IC in order to calibrate the buffer.

Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic may be configured to selectively couple a signal received on a second external pin of the IC either via the buffer to the first external pin of the IC in order to calibrate the buffer.

Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic is configured to selectively couple a signal received on a second external pin of the IC either via the buffer to the first external pin of the IC in order to calibrate the buffer.

Abstract: A multiphase power controller that generates a set of switching control signals to drive a set of power stages. The set of power stages generates an output that drives a load. The multiphase power controller includes a summer to generate an equivalent voltage representative of a sum of inductor currents from each of an inductor in the set of power stages. A threshold generation circuit generates a set of threshold signals in response to a set of control outputs and a reference. A set of comparators generates the set of control outputs, in response to the equivalent voltage and the set of threshold signals. A state machine generates a set of phase control signals in response to the set of control outputs. The set of control outputs changes a number of the set of switching control signals.

Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic may be configured to selectively couple a signal received on a second external pin of the IC either via the buffer to the first external pin of the IC in order to calibrate the buffer.