Abstract: This disclosure describes a storage aggregator controller with metadata computation control. The storage aggregator controller communicates, via a host interface, over a computer network with one or more remote hosts, and also communicates, via a storage device interface, with a plurality of local storage devices, which are separate from the remote host(s) and which have respective non-volatile memories. The storage aggregator controller manages the local storage devices for storage or retrieval of media objects. The storage aggregator controller also governs a selective computation, at aggregator control circuitry or at a storage device controller of one or more of the storage devices, of metadata that defines content characteristics of the media objects that are retrieved from the plurality of storage devices or that are received from the one or more hosts over the computer network for storage in the plurality of storage devices.

Abstract: Embodiments described herein provide improved methods and systems for generating metadata for media objects at a computational engine (such as an artificial intelligence engine) within the storage edge controller, and for storing and using such metadata, in data processing systems.

Abstract: A system for generating a queryable structured document from an unstructured document using a machine learning model is provided. The system (i) identifies breakpoints in the unstructured document, (ii) segments the unstructured document into one or more fragments based on identified breakpoints, (iii) classifies the one or more fragments as one or more title fragments or one or more non-title fragments based on a sequence of a position of words used in each fragment of the one or more fragments, (iv) constructs a data tree using the one or more title fragments and the one or more non-title fragments as a node of the data tree; (v) assigns one or more vectors to each node of the data tree, and (vi) generates a structured document by providing matrix representation for each node of the data tree.

Abstract: Methods and apparatus for matrix and vector storage and operations are disclosed. Vectors and matrices may be represented differently to further enhance performance of operations. Exemplary embodiments compress sparse neural network data structures based on actual, non-null, connectivity (rather than all possible connections). This greatly reduces storage requirements as well as computational complexity. In some variants, the compression and reduction in complexity is sized to fit within the memory footprint and processing capabilities of a core. The exemplary compression schemes represent sparse matrices with links to compressed column data structures, where each compressed column data structure only stores non-null entries to optimize column-based lookups of non-null entries. Similarly, sparse vector addressing skips nulled entries to optimize for vector-specific non-null multiply-accumulate operations.

Abstract: Embodiments described herein provide improved methods and systems for generating metadata for media objects at a computational engine (such as an artificial intelligence engine) within the storage edge controller, and for storing and using such metadata, in data processing systems.

Abstract: Embodiments described herein provide improved methods and systems for generating metadata for media objects at a computational engine (such as an artificial intelligence engine) within the storage edge controller, and for storing and using such metadata, in data processing systems.

Abstract: A system for generating a queryable structured document from an unstructured document using a machine learning model is provided. The system (i) identifies breakpoints in the unstructured document, (ii) segments the unstructured document into one or more fragments based on identified breakpoints, (iii) classifies the one or more fragments as one or more title fragments or one or more non-title fragments based on a sequence of a position of words used in each fragment of the one or more fragments, (iv) constructs a data tree using the one or more title fragments and the one or more non-title fragments as a node of the data tree; (v) assigns one or more vectors to each node of the data tree, and (vi) generates a structured document by providing matrix representation for each node of the data tree.

Abstract: This disclosure describes a storage aggregator controller with metadata computation control. The storage aggregator controller communicates, via a host interface, over a computer network with one or more remote hosts, and also communicates, via a storage device interface, with a plurality of local storage devices, which are separate from the remote host(s) and which have respective non-volatile memories. The storage aggregator controller manages the local storage devices for storage or retrieval of media objects. The storage aggregator controller also governs a selective computation, at aggregator control circuitry or at a storage device controller of one or more of the storage devices, of metadata that defines content characteristics of the media objects that are retrieved from the plurality of storage devices or that are received from the one or more hosts over the computer network for storage in the plurality of storage devices.

Abstract: Embodiments described herein provide improved methods and systems for generating metadata for media objects at a computational engine (such as an artificial intelligence engine) within the storage edge controller, and for storing and using such metadata, in data processing systems.

Abstract: A non-fighting fully clocked scan latch is described that is dynamically configurable to support both logic data latching and scan data latching. The described scan latch circuit design reduces a load placed on a logic data latch portion of the described circuit by a scan latch portion of the described circuit, and thereby increases the speed of the described scan latch to that of an output latch without scan capability. Power required to drive the described scan latch is reduced by clocking the circuit to avoid fighting and by reducing the number of transistors included in transistor stacks internal to the scan latch. By reducing drive power requirements, eliminating internal latch fighting, and increasing latch response, a versatile scan latch is achieved that may be successfully implemented in a wide range of circuits despite the use of different supply drive voltage, threshold voltage, source-to-drain voltage, and transistor technology combinations.

Abstract: An output storage latch within a combinational logic circuit may be adapted to form a scan flip-flop latch that supports both functional operation and scan chain testing of a combinational logic matrix included in the combinational logic circuit. A described master/slave clock approach allows the scan flip-flop latch to support receiving into a scan chain a sequence of test input data, execution of combinational logic matrix testing based on the test input data, and sequentially outputting test results to a test result register for comparison with expected results. The described scan flip-flop latch may be used along side unaltered output storage latches thereby allowing flexibility with respect to the number and placement scan chain test points within an integrated circuit. Use of the described dual-use scan flip-flop latch results in a less complex circuit design, reduced circuit area requirements and improved reliability.

Abstract: A non-fighting fully clocked scan latch is described that is dynamically configurable to support both logic data latching and scan data latching. The described scan latch circuit design reduces a load placed on a logic data latch portion of the described circuit by a scan latch portion of the described circuit, and thereby increases the speed of the described scan latch to that of an output latch without scan capability. Power required to drive the described scan latch is reduced by clocking the circuit to avoid fighting and by reducing the number of transistors included in transistor stacks internal to the scan latch. By reducing drive power requirements, eliminating internal latch fighting, and increasing latch response, a versatile scan latch is achieved that may be successfully implemented in a wide range of circuits despite the use of different supply drive voltage, threshold voltage, source-to-drain voltage, and transistor technology combinations.

Abstract: A output storage latch within a combinational logic circuit may be adapted to form a scan flip-flop latch that supports both functional operation and scan chain testing of a combinational logic matrix included in the combinational logic circuit. A described master/slave clock approach allows the scan flip-flop latch to support receiving into a scan chain a sequence of test input data, execution of combinational logic matrix testing based on the test input data, and sequentially outputting test results to a test result register for comparison with expected results. The described scan flip-flop latch may be used along side unaltered output storage latches thereby allowing flexibility with respect to the number and placement scan chain test points within an integrated circuit. Use of the described dual-use scan flip-flop latch results in a less complex circuit design, reduced circuit area requirements and improved reliability.

Abstract: A non-fighting fully clocked scan latch is described that is dynamically configurable to support both logic data latching and scan data latching. The described scan latch circuit design reduces a load placed on a logic data latch portion of the described circuit by a scan latch portion of the described circuit, and thereby increases the speed of the described scan latch to that of an output latch without scan capability. Power required to drive the described scan latch is reduced by clocking the circuit to avoid fighting and by reducing the number of transistors included in transistor stacks internal to the scan latch. By reducing drive power requirements, eliminating internal latch fighting, and increasing latch response, a versatile scan latch is achieved that may be successfully implemented in a wide range of circuits despite the use of different supply drive voltage, threshold voltage, source-to-drain voltage, and transistor technology combinations.

Abstract: A output storage latch within a combinational logic circuit may be adapted to form a scan flip-flop latch that supports both functional operation and scan chain testing of a combinational logic matrix included in the combinational logic circuit. A described master/slave clock approach allows the scan flip-flop latch to support receiving into a scan chain a sequence of test input data, execution of combinational logic matrix testing based on the test input data, and sequentially outputting test results to a test result register for comparison with expected results. The described scan flip-flop latch may be used along side unaltered output storage latches thereby allowing flexibility with respect to the number and placement scan chain test points within an integrated circuit. Use of the described dual-use scan flip-flop latch results in a less complex circuit design, reduced circuit area requirements and improved reliability.

Abstract: A output storage latch within a combinational logic circuit may be adapted to form a scan flip-flop latch that supports both functional operation and scan chain testing of a combinational logic matrix included in the combinational logic circuit. A described master/slave clock approach allows the scan flip-flop latch to support receiving into a scan chain a sequence of test input data, execution of combinational logic matrix testing based on the test input data, and sequentially outputting test results to a test result register for comparison with expected results. The described scan flip-flop latch may be used along side unaltered output storage latches thereby allowing flexibility with respect to the number and placement scan chain test points within an integrated circuit. Use of the described dual-use scan flip-flop latch results in a less complex circuit design, reduced circuit area requirements and improved reliability.

Abstract: A output storage latch within a combinational logic circuit may be adapted to form a scan flip-flop latch that supports both functional operation and scan chain testing of a combinational logic matrix included in the combinational logic circuit. A described master/slave clock approach allows the scan flip-flop latch to support receiving into a scan chain a sequence of test input data, execution of combinational logic matrix testing based on the test input data, and sequentially outputting test results to a test result register for comparison with expected results. The described scan flip-flop latch may be used along side unaltered output storage latches thereby allowing flexibility with respect to the number and placement scan chain test points within an integrated circuit. Use of the described dual-use scan flip-flop latch results in a less complex circuit design, reduced circuit area requirements and improved reliability.