Abstract: A circuit including a memory cell, a pair of bit lines, a precharge circuit, a multiplexer, and a pull-up circuit is provided herein. The bit lines are coupled to the memory cell. The precharge circuit is coupled between the bit lines and configured to precharge each of the bit lines to approximately a first supply voltage to begin the write operation. The multiplexer is configured to select which bit line is a zero bit driven to a low logic level during the write operation and after the precharge circuit is turned off. After the write operation begins, the pull-up circuit is coupled to the bit lines and configured to select which bit line is a non-zero bit line driven to a high logic level.

Abstract: A self-time circuitry is coupled to a first power rail to receive a first voltage and a second power rail to receive a second voltage. The self-time circuitry includes a tracking control circuit which generates a first tracking signal at the first voltage and a second tracking signal at the second voltage. In response to a memory access request, a first number of dummy discharge cells (DDCs) in a first DDC group are activated according to the first tracking signal to discharge a dummy bit line (DBL), and a second number of DDCs in a second DDC group are activated according to the second tracking signal to discharge the DBL. The DBL mimics operations of a bit line in a memory cell array and the DDCs in the first DDC group and the second DDC group mimic operations of bit cells in the memory cell array.

Abstract: A self-time circuitry is coupled to a first power rail to receive a first voltage and a second power rail to receive a second voltage. The self-time circuitry includes a tracking control circuit which generates a first tracking signal at the first voltage and a second tracking signal at the second voltage. In response to a memory access request, a first number of dummy discharge cells (DDCs) in a first DDC group are activated according to the first tracking signal to discharge a dummy bit line (DBL), and a second number of DDCs in a second DDC group are activated according to the second tracking signal to discharge the DBL. The DBL mimics operations of a bit line in a memory cell array and the DDCs in the first DDC group and the second DDC group mimic operations of bit cells in the memory cell array.

Abstract: Control circuits for memory devices are described. The control circuits may be configured such that the duration of the pulses delivered to the sense amplifiers increases with increasing parasitic RC delays. That is, the larger the parasitic RC delay along a line connecting a drive circuit to the sense amplifiers, the larger the duration of the pulses delivered. In some embodiments, a feedback line may be inserted between the end of the output signal line and the drive circuit to route the control pulses back to the drive circuit. The drive circuit may be arranged such that the duration of the pulses with which the sense amplifiers are driven depends on the delay experienced along the feedback line. In this way, the longer the RC delay arising along the feedback line, the larger the durations of the pulses.

Abstract: Control circuits for memory devices are described. The control circuits may be configured such that the duration of the pulses delivered to the sense amplifiers increases with increasing parasitic RC delays. That is, the larger the parasitic RC delay along a line connecting a drive circuit to the sense amplifiers, the larger the duration of the pulses delivered. In some embodiments, a feedback line may be inserted between the end of the output signal line and the drive circuit to route the control pulses back to the drive circuit. The drive circuit may be arranged such that the duration of the pulses with which the sense amplifiers are driven depends on the delay experienced along the feedback line. In this way, the longer the RC delay arising along the feedback line, the larger the durations of the pulses.

Abstract: Various implementations described herein are directed to an integrated circuit having high density memory architecture. The integrated circuit may include a plurality of bank arrays having multiple segments of bitcells configured to share local control. The integrated circuit may include a plurality of control lines coupling the local control to each of the multiple segments of bitcells. In some instances, during activation of a segment of bitcells by the local control via one of the control lines, another segment of bitcells may be deactivated by the local control via another of the control lines.

Abstract: Various implementations described herein are directed to an integrated circuit for read-write contention. The integrated circuit may include a memory circuit having multiple ports configured to receive data signals corresponding to each port. The integrated circuit may include a contention override circuit providing a contention override signal for each port based on detecting a read-write contention between the ports. The integrated circuit may include a write circuit having multiple passgates for each port including write passgates and contention passgates for each port. The write passgates may be input with data signals from corresponding ports. The contention passgates may be input with data signals from opposing ports based on opposing contention override signals.

Abstract: Various implementations described herein are directed to an integrated circuit for read-write contention. The integrated circuit may include a memory circuit having multiple ports configured to receive data signals corresponding to each port. The integrated circuit may include a contention override circuit providing a contention override signal for each port based on detecting a read-write contention between the ports. The integrated circuit may include a write circuit having multiple passgates for each port including write passgates and contention passgates for each port. The write passgates may be input with data signals from corresponding ports. The contention passgates may be input with data signals from opposing ports based on opposing contention override signals.

Abstract: A circuit generates low-skew true and complement output signals from an input signal using an inverter, true signal generation circuitry, and complement signal generation circuitry. The inverter operates between a high-voltage reference source (VDD) and a low-voltage reference source (VSS) and inverts the input signal to generate a delayed complement input signal. The true signal generation circuitry, which comprises a p-type transistor in series with an n-type transistor, (i) operates between (a) one of VDD and VSS and (b) one of the true input signal and the complement input signal and (ii) generates a true output signal. The complement signal generation circuitry, which also comprises p-type transistor in series with an n-type transistor, (i) operates between (a) one of VDD and VSS and (b) one of the true input signal and the complement input signal and (ii) generates a complement output signal.

Abstract: A memory device includes a memory array comprising memory cells, sense amplifiers configured to sense data stored in the memory cells of the memory array, and control circuitry configured to generate a plurality of separate sense amplifier control signals for application to respective control inputs of respective ones of the sense amplifiers. For example, the memory device may comprise a row of dummy memory cells each coupled to a dummy wordline. In such an arrangement, the control circuitry may comprise a plurality of logic gates coupled to respective ones of the dummy memory cells, with each such logic gate configured to generate a corresponding one of the separate sense amplifier control signals for a corresponding one of the sense amplifiers as a function of a data transition at a bitline of the corresponding dummy memory cell. The separate sense amplifier control signals may comprise respective sense amplifier enable signals.

Abstract: A circuit generates low-skew true and complement output signals from an input signal using an inverter, true signal generation circuitry, and complement signal generation circuitry. The inverter operates between a high-voltage reference source (VDD) and a low-voltage reference source (VSS) and inverts the input signal to generate a delayed complement input signal. The true signal generation circuitry, which comprises a p-type transistor in series with an n-type transistor, (i) operates between (a) one of VDD and VSS and (b) one of the true input signal and the complement input signal and (ii) generates a true output signal. The complement signal generation circuitry, which also comprises p-type transistor in series with an n-type transistor, (i) operates between (a) one of VDD and VSS and (b) one of the true input signal and the complement input signal and (ii) generates a complement output signal.

Abstract: A latch circuit comprises true and complement data nodes. During a setup period of a latching operation, true node setup circuitry draws the true data node toward an input data signal in parallel with complement node setup circuitry drawing the complement node upward toward a high-voltage reference source (VDD) when the data signal is low or downward toward a low-voltage reference source (VSS) when the data signal is high. After the setup period, true and complement clock signals are used as control signals to turn the setup circuitry off and amplification circuitry on. The amplification circuitry, which comprises a pair of cross-coupled inverters coupled between VDD and VSS, is capable of resolving relatively small voltage differentials between the true and complement nodes by pulling the true node (i) upward toward VDD when the data signal is high and (ii) downward toward VSS when the data signal is low.

Abstract: A memory device includes a memory array comprising a plurality of memory cells, a plurality of sense amplifiers configured to sense data stored in the memory cells of the memory array, a dummy wordline coupled to respective enable inputs of the sense amplifiers, a dummy wordline return, a dummy bitline, a dummy sense amplifier having an input coupled to the dummy bitline, and control circuitry coupled to the output of the dummy sense amplifier and the dummy wordline return. The control circuitry has a first configuration for generating a reset signal based at least in part on a signal at the output of the dummy sense amplifier in a read mode of operation, and has a second configuration different than the first configuration for generating the reset signal based at least in part on a signal on the dummy wordline return in a write mode of operation.

Abstract: A memory device includes a memory array comprising a plurality of memory cells, a plurality of sense amplifiers configured to sense data stored in the memory cells of the memory array, a dummy wordline coupled to respective enable inputs of the sense amplifiers, a dummy wordline return, a dummy bitline, a dummy sense amplifier having an input coupled to the dummy bitline, and control circuitry coupled to the output of the dummy sense amplifier and the dummy wordline return. The control circuitry has a first configuration for generating a reset signal based at least in part on a signal at the output of the dummy sense amplifier in a read mode of operation, and has a second configuration different than the first configuration for generating the reset signal based at least in part on a signal on the dummy wordline return in a write mode of operation.

Abstract: Disclosed is an adaptive negative bit-line boost write assist technique in which coupling capacitance scales with the number of rows and thereby maintains a constant negative bit-line level. The change in the coupling capacitance in neighboring signals as the height increases is utilized. The change is utilized for negative bit-line voltage generation.

Abstract: A memory device includes a memory array comprising memory cells, sense amplifiers configured to sense data stored in the memory cells of the memory array, and control circuitry configured to generate a plurality of separate sense amplifier control signals for application to respective control inputs of respective ones of the sense amplifiers. For example, the memory device may comprise a row of dummy memory cells each coupled to a dummy wordline. In such an arrangement, the control circuitry may comprise a plurality of logic gates coupled to respective ones of the dummy memory cells, with each such logic gate configured to generate a corresponding one of the separate sense amplifier control signals for a corresponding one of the sense amplifiers as a function of a data transition at a bitline of the corresponding dummy memory cell. The separate sense amplifier control signals may comprise respective sense amplifier enable signals.

Abstract: A sensing circuit for use in a memory including memory cells and at least one bitline coupled with the memory cells includes first and second sense amplifiers and a controller coupled with the sense amplifiers. The first sense amplifier is adapted to read a selected one of the memory cells coupled to the first sense amplifier via a corresponding bitline. The second sense amplifier is adapted to read a selected one of the memory cells coupled to the second sense amplifier via a corresponding bitline. The controller selectively connects one of the first and second sense amplifiers in an active path of the memory in a manner which enables one of the sense amplifiers to be operative in a precharge mode and another of the sense amplifiers to be concurrently operative in a sensing mode during a given memory cycle.