Patents by Inventor Manisha DUTTA

Manisha DUTTA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250006667
    Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a package for wideband sub-terahertz communication, where the package includes a mixer and an amplifier, such as a power amplifier or a low noise amplifier, that are implemented within a layer of III-V material. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 27, 2023
    Publication date: January 2, 2025
    Inventors: Georgios PANAGOPOULOS, Steven CALLENDER, Richard GEIGER, Georgios C. DOGIAMIS, Manisha DUTTA, Stefano PELLERANO
  • Publication number: 20250006719
    Abstract: Example antenna module includes antenna units provided over an antenna unit support, and ICs communicatively coupled to various antenna units. The ICs are arranged in two or more subsets of one or more ICs in each subset, where an individual IC belongs to only one subset, different subsets are in different layers with respect to the antenna unit support, and an average pitch of projections of all of the ICs onto a plane parallel to the antenna unit support is substantially equal to, or smaller, than an average pitch of the antenna units. When an average width of the ICs is larger than the average pitch of the antenna units, arranging the ICs in two or more subsets in different layers means that at least one of the ICs of one subset partially overlaps with at least one of the ICs of another subset.
    Type: Application
    Filed: June 27, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Georgios Panagopoulos, Richard Geiger, Steven Callender, Georgios Dogiamis, Manisha Dutta, Stefano Pellerano
  • Publication number: 20240429117
    Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for reducing the capacitance of a package that includes a die by at least partially surrounding the die within a mold compound and a dielectric material with different dielectric constants. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 20, 2023
    Publication date: December 26, 2024
    Inventors: Harshit DHAKAD, Georgios C. DOGIAMIS, Georg SEIDEMANN, Bernd WAIDHAS, Thomas WAGNER, Manisha DUTTA, Michael LANGENBUCH
  • Publication number: 20240429221
    Abstract: Glass layers and capacitors for use with integrated circuit packages are disclosed. An example integrated circuit (IC) package includes a semiconductor die, a glass layer, and a capacitor electrically coupled to the semiconductor die, at least one side of the capacitor enclosed by the glass layer, the capacitor positioned closer to the glass layer than the semiconductor die is to the glass layer.
    Type: Application
    Filed: June 22, 2023
    Publication date: December 26, 2024
    Inventors: Bernd Waidhas, Thomas Wagner, Georg Seidemann, Nicolas Richaud, Manisha Dutta, Georgios Dogiamis, Harshit Dhakad, Michael Langenbuch