Abstract: Systems and methods are described herein for dynamic debug logging during application runtime. In an example, a wrapper can be added to the code for functions of the application. During runtime, the wrapper can cause the functions to retain certain debug data. In one example, a function call graph can be constructed, which can include all the possible function call paths for the application. When an error occurs, if the application does not have a stack trace tool or API available, the application can use the function call graph to determine all possible function call paths between the entrant function and the errored function. If an application does have a stack trace tool or API, then the application can retrieve the actual function call path that led to the error. The application can enable a debug flag in the wrapper for each function in the function call path, which can cause those functions to log runtime debug data.

Abstract: Systems and methods are described herein for dynamic debug logging during application runtime. In an example, a wrapper can be added to the code for functions of the application. During runtime, the wrapper can cause the functions to retain certain debug data. In one example, a function call graph can be constructed, which can include all the possible function call paths for the application. When an error occurs, if the application does not have a stack trace tool or API available, the application can use the function call graph to determine all possible function call paths between the entrant function and the errored function. If an application does have a stack trace tool or API, then the application can retrieve the actual function call path that led to the error. The application can enable a debug flag in the wrapper for each function in the function call path, which can cause those functions to log runtime debug data.

Abstract: Systems and methods for improving seek times in a read channel performing a read operation on a disk drive are disclosed. The method includes extrapolating, based on initial filter settings corresponding to a first user-data region or a first servo-data region and tracked settings varying over time, a proportionality constant for the programmable analog filter, in response to determining a new target frequency for the programmable analog filter corresponding to a second user-data region or a second servo-data region, computing new filter settings for the programmable analog filter based on the extrapolated proportionality constant, and transmitting, to the programmable analog filter, the computed new filter settings corresponding to the new target frequency of the second user-data region or the second servo-data region.

Abstract: A method includes receiving data for a desired output frequency of an output clock of a phase locked loop (PLL) circuit. The method includes determining a preset value for a digitally controlled oscillator (DCO) of the PLL circuit, determining first gain coefficients and second gain coefficients for a filter of the PLL circuit, and determining ratio values for a divider circuit of the PLL circuit based on the data. The method includes providing the preset value to the DCO, the first gain coefficients to the filter, and the ratio values to the divider circuit while the PLL circuit operates in an open-loop configuration. The method includes subsequently operating the PLL circuit in a closed-loop configuration by connecting the filter to the DCO, and providing the second gain coefficients to the filter in response to detecting a phase lock of the PLL circuit operating in the closed-loop configuration.

Abstract: During operation of an analog filter having one or more filter stages is configured to operate in a first configuration. Configuring the analog filter to operate in the first filter configuration includes configuring one or both of i) a filter response of the analog filter and ii) a filter bandwidth of the analog filter. A first set of one or more direct current (DC) offset correction codes corresponding to the first filter configuration are retrieved from a memory. The one or more DC offset correction codes in the first set are converted to one or more first analog DC offset correction signals. While operating the analog filter configured in the first configuration, the one or more first analog DC offset correction signals are applied to the one or more filter stages of the analog filter.

Abstract: A phase lock loop circuit includes a phase frequency detector, a voltage controlled oscillator, a phase interpolator, a clock signal selector, a selection module, a multiplexer, and a divider. The phase frequency detector compares phases of a reference clock and frequency divided output signals and generates an error signal. The voltage controlled oscillator, based on the error signal, generates a phase lock loop output signal and output clock signals. The phase interpolator phase interpolates the output clock signals to generate an interpolator output signal. The clock signal selector selects one of the output clock signals. The selection module generates a selection signal based on states of the interpolator output and selected output clock signals. The multiplexer, based on the selection signal, selects the interpolator output signal or the selected output clock signal. The divider frequency divides an output of the multiplexer to provide the frequency divided output signal.

Abstract: A digital locking loop circuit (DLLC), such as a digital phase-locked loop or digital delay-locked loop, includes a digitally-controlled frequency generator, a digital loop filter configured to output a digital control signal for the frequency generator, and a multi-stage time-to-digital converter to detect phase error between an input reference clock signal and an output signal fed back from the frequency generator, to adjust the digitally-controlled frequency generator to decrease the phase error. Each phase-error detection stage detects a phase error component at a respective resolution, and combinatorial logic combines the components into a phase error signal. The plurality of stages may operate in parallel to provide different portions of the phase error signal. The DLLC may include a fractional phase interpolator to adjust the target frequency by a fractional amount, and one of the stages includes conversion circuitry to compensate for a fractional phase. A method also is provided.

Abstract: In some implementations, a system includes a phase locked loop (PLL) circuit and a digital control unit. The PLL circuit includes a digital loop filter, a digitally controlled oscillator (DCO), and a divider circuit. The digital control unit is configured determine a preset value for the DCO; determine initial gain coefficients and final gain coefficients for the digital loop filter; determine N/R values for the divider circuit; while the PLL circuit is operating in an open-loop configuration, provide the preset value to the DCO, the initial gain coefficients to the digital loop filter, and the N/R values to the divider circuit; after providing the preset value, initial gain coefficients, and N/R values, initiate operation of the PLL circuit in the closed-loop configuration; and in response to detection of a phase lock of the PLL circuit operating in the closed-loop configuration, provide the final gain coefficients to the digital loop filter.

Abstract: A digital locking loop circuit (DLLC), such as a digital phase-locked loop or digital delay-locked loop, includes a digitally-controlled frequency generator, a digital loop filter configured to output a digital control signal for the frequency generator, and a multi-stage time-to-digital converter to detect phase error between an input reference clock signal and an output signal fed back from the frequency generator, to adjust the digitally-controlled frequency generator to decrease the phase error. Each phase-error detection stage detects a phase error component at a respective resolution, and combinatorial logic combines the components into a phase error signal. The plurality of stages may operate in parallel to provide different portions of the phase error signal. The DLLC may include a fractional phase interpolator to adjust the target frequency by a fractional amount, and one of the stages includes conversion circuitry to compensate for a fractional phase. A method also is provided.