Patents by Inventor Manivannan Balu

Manivannan Balu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220187788
    Abstract: An apparatus includes a debugger circuit, debug pins, and a test controller circuit. The test controller circuit is configured to, in a programming mode, determine a subset of the debug pins used in programming the apparatus. The test controller circuit is further configured to save a designation of the subset of the debug pins. The test controller circuit is further configured to, in a test mode subsequent to the programming mode, use the designation to route the subset of the debug pins used in programming the apparatus to the debugger circuit for debug input and output with the server.
    Type: Application
    Filed: November 19, 2021
    Publication date: June 16, 2022
    Applicant: Microchip Technology Incorporated
    Inventors: Stephen Bowling, Manivannan Balu, Timothy Phoenix, Sankar Rangarajan
  • Patent number: 10860408
    Abstract: A semiconductor die includes a feedback path coupled to the output pin, and an integrity monitor circuit (IMC). The output pin is communicatively coupled to the logic. The IMC is configured to receive a data value. The IMC is further configured to receive measured data value from the output pin routed through the feedback path, compare the data value and the measured data value, and, based on the comparison, determine whether an error has occurred.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: December 8, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Stephen Bowling, Igor Wojewoda, Manivannan Balu
  • Publication number: 20190340047
    Abstract: A semiconductor die includes a feedback path coupled to the output pin, and an integrity monitor circuit (IMC). The output pin is communicatively coupled to the logic. The IMC is configured to receive a data value. The IMC is further configured to receive measured data value from the output pin routed through the feedback path, compare the data value and the measured data value, and, based on the comparison, determine whether an error has occurred.
    Type: Application
    Filed: May 3, 2018
    Publication date: November 7, 2019
    Applicant: Microchip Technology Incorporated
    Inventors: Stephen Bowling, Igor Wojewoda, Manivannan Balu
  • Patent number: 10352998
    Abstract: In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: July 16, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Stephen Bowling, Igor Wojewoda, Dereck Fernandes, Manivannan Balu, Yong Yuenyongsgool, Timothy Phoenix, Steve Bradley
  • Publication number: 20190113568
    Abstract: In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.
    Type: Application
    Filed: October 17, 2017
    Publication date: April 18, 2019
    Applicant: Microchip Technology Incorporated
    Inventors: Stephen Bowling, Igor Wojewoda, Dereck Fernandes, Manivannan Balu, Yong Yuenyongsgool, Timothy Phoenix, Steve Bradley