Patents by Inventor Manjanaika CHANDRANAIKA

Manjanaika CHANDRANAIKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DECOUPLING CAPACITOR ARCHITECTURE
    Publication number: 20240088014
    Abstract: In certain aspects, a chip includes first source/drain contacts formed over a first oxide diffusion (OD), and first gates, wherein each of the first gates is disposed between a respective pair of the first source/drain contacts. The chip also includes a first bridge coupling a first one of the first source/drain contacts, a first one of the first gates, and a second one of the first source/drain contacts. The chip also includes a first metal routing coupled to the first one of the first source/drain contacts, and a second metal routing coupled to the second one of the first source/drain contacts.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 14, 2024
    Inventors: Keyurkumar Karsanbhai KANSAGRA, Manjanaika CHANDRANAIKA, Ankit GUPTA, Kamesh MEDISETTI, Akhtar ALAM
  • INTEGRATED CIRCUIT CELL WITH DUAL ROW, BACK-TO-BACK, TRANSISTOR BODY TIES
    Publication number: 20240038760
    Abstract: An integrated circuit (IC), including a first row of cells including a first set of one or more complementary metal oxide semiconductor (CMOS) signal processing cells including a first diffusion region; a second row of cells including a second set of one or more CMOS signal processing cells including a second diffusion region; and a first body tie electrically coupling a first voltage rail to the first and second diffusion regions.
    Type: Application
    Filed: August 1, 2022
    Publication date: February 1, 2024
    Inventors: Manjanaika CHANDRANAIKA, Parissa NAJDESAMII, Kamesh MEDISETTI, Iranagouda Shivanagouda NAGANAGOUDRA