Abstract: In one embodiment, a system determines a difference in time between a local time source and a time of a GPS sensor. The system determines a max limit in difference and a max recovery increment or max recovery time interval for a smooth time source recovery. The system determines that the difference between the local time source and a time of the GPS sensor to be less than the max limit. The system plans a smooth recovery of the time source to converge the local time source to a time of the GPS sensor within the max recovery time interval. The system generates a timestamp based on the recovered time source to timestamp sensor data for a sensor unit of the ADV.

Abstract: A sensor unit used in an ADV includes a sensor interface that can be coupled to cameras mounted on the ADV. The sensor unit further includes a host interface that can be coupled to a host system. The host system is configured to perceive a driving environment surrounding the ADV based on at least image data obtained from the cameras and to plan a path to autonomously drive the ADV. The sensor unit further includes one or more data acquisition modules corresponding to the cameras. Each data acquisition module includes a pixel alignment module and a frame processing module. The pixel alignment module is configured to reformat pixels of image data from an original format associated with the corresponding camera to a predetermined format. The frame processing module is configured to generate an image frame based on the image data and to transmit the image frame to the host system.

Abstract: A sensor unit includes a sensor interface coupled to a number of sensors and a host interface coupled to a host system utilized to autonomously drive the vehicle. The sensor unit further includes sensor control modules corresponding to the sensors. Each sensor control module includes delay time control logic, delay adjustment logic, and a trigger signal generator. The delay time control logic is to receive a pulse time adjustment (PTA) value from the host system. The delay adjustment logic is to receive a trigger time adjustment (TTA) value from the host system. The delay adjustment logic is to modify timing of at least a portion of the pulses of a pulse signal based on the PTA value and the TTA value. The trigger signal generator is to generate a trigger signal based on the modified pulse signal and to transmit the trigger signal to a corresponding sensor.

Abstract: According to one embodiment, a source code is parsed to identify a first routine to perform a first function and a second routine to perform a second function. A control signaling topology is determined between the first routine and the second routine based on one or more statements associated with the first routine and the second routine defined in the source code. A first logic block is allocated describing a first hardware configuration representing the first function of the first routine. A second logic block is allocated describing a second hardware configuration representing the second function of the second routine. A register-transfer level (RTL) netlist is generated based on the first logic block and the second logic block. The second logic block is to perform the second function dependent upon the first function performed by the first logic block based on the control signaling topology.

Abstract: According to one embodiment, a source code is parsed to identify a first routine to perform a first function and a second routine to perform a second function. A control signaling topology is determined between the first routine and the second routine based on one or more statements associated with the first routine and the second routine defined in the source code. A first logic block is allocated describing a first hardware configuration representing the first function of the first routine. A second logic block is allocated describing a second hardware configuration representing the second function of the second routine. A register-transfer level (RTL) netlist is generated based on the first logic block and the second logic block. The second logic block is to perform the second function dependent upon the first function performed by the first logic block based on the control signaling topology.