Abstract: A semiconductor device may include a lower insulating layer on a substrate, a data storage pattern disposed on the lower insulating layer, a cell insulating layer disposed on the lower insulating layer to cover the data storage pattern, a cell conductive line disposed on the data storage pattern, and a capping insulating layer interposed between a side surface of the data storage pattern and the cell insulating layer. The cell conductive line may include a first portion adjacent to the data storage pattern and a second portion on the first portion, and the capping insulating layer may be extended to a side surface of the first portion.

Abstract: A magnetoresistive memory device includes a lower contact structure on a substrate, a data storage structure comprising a first pattern structure, a tunnel barrier pattern, and a second pattern structure, which are sequentially stacked on the lower contact structure, a first spacer structure covering a side wall of the first pattern structure, a second spacer structure apart from the first spacer structure in a vertical direction and covering a side wall of the second pattern structure, an isolation insulating layer in contact with a side wall of the tunnel barrier pattern, and a protective insulating layer covering the data storage structure, the first spacer structure, the second spacer structure, and the isolation insulating layer.

Abstract: A method of manufacturing a memory device includes sequentially forming a first magnetization layer, a tunnel barrier layer, and a second magnetization layer on each other; forming a magnetic tunnel junction structure by patterning the first magnetization layer, the tunnel barrier layer, and the second magnetization layer; forming a sidewall metal layer by etching a portion of a redeposited metal covering a sidewall of the magnetic tunnel junction structure; performing an oxidizing operation that includes oxidizing an exposed surface of the sidewall metal layer to provide an oxidized sidewall metal layer; and performing an irradiating operation that includes irradiating an ion beam towards the oxidized sidewall metal layer. A sidewall insulating layer covering a sidewall of the magnetic tunnel junction structure is formed by alternately performing the oxidizing operation and the irradiating operation two or more times.

Abstract: A method of manufacturing a magnetoresistive memory device includes forming an isolation layer and a via contact on a substrate, the via contact having a sidewall surrounded by the isolation layer, forming a memory stack on the isolation layer and the via contact, the memory stack comprising a lower electrode layer, a magnetic tunnel junction layer, and an upper electrode layer, forming a plurality of memory cells by patterning the memory stack, forming a metal material redeposited layer during the ion beam etching process on an upper surface of the isolation layer, and forming an insulating liner on the plurality of memory cells. The insulating liner comprises a first portion covering the plurality of memory cells, the first portion comprising a first oxide, and a second portion formed by oxidation of at least a portion of the metal material redeposited layer, the second portion comprising a second oxide.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, interconnection lines on the cell region and the peripheral region, the interconnection lines being spaced apart from the substrate in a first direction perpendicular to a top surface of the substrate, a lower insulating layer on the cell region and the peripheral region, the lower insulating layer covering the interconnection lines, and a top surface of the lower insulating layer on the cell region being at a lower height than top surfaces of uppermost interconnection lines of the interconnection lines, and data storage patterns on the lower insulating layer on the cell region, the data storage patterns being horizontally spaced apart from each other, and the data storage patterns being connected directly to the top surfaces of the uppermost interconnection lines on the cell region.

Abstract: A magnetoresistive random access memory device includes a substrate; conductive patterns on the substrate; an insulating interlayer covering the conductive patterns; a lower electrode contact passing through the insulating interlayer, the lower electrode contact contacting the conductive pattern; a lower electrode on the lower electrode contact, the lower electrode including a rounded sidewall; and a memory structure on the lower electrode, the memory structure including a stacked MTJ structure and upper electrode, wherein a width of the lower electrode increases from a lower portion to an upper portion, the memory structure has a sidewall slope such that a width of the memory structure increases from an upper portion to a lower portion, and at least a portion of a sidewall of the lower electrode is covered by the first insulating interlayer.

Abstract: A method of manufacturing a memory device includes sequentially forming a first magnetization layer, a tunnel barrier layer, and a second magnetization layer on each other; forming a magnetic tunnel junction structure by patterning the first magnetization layer, the tunnel barrier layer, and the second magnetization layer; forming a sidewall metal layer by etching a portion of a redeposited metal covering a sidewall of the magnetic tunnel junction structure; performing an oxidizing operation that includes oxidizing an exposed surface of the sidewall metal layer to provide an oxidized sidewall metal layer; and performing an irradiating operation that includes irradiating an ion beam towards the oxidized sidewall metal layer. A sidewall insulating layer covering a sidewall of the magnetic tunnel junction structure is formed by alternately performing the oxidizing operation and the irradiating operation two or more times.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, interconnection lines on the cell region and the peripheral region, the interconnection lines being spaced apart from the substrate in a first direction perpendicular to a top surface of the substrate, a lower insulating layer on the cell region and the peripheral region, the lower insulating layer covering the interconnection lines, and a top surface of the lower insulating layer on the cell region being at a lower height than top surfaces of uppermost interconnection lines of the interconnection lines, and data storage patterns on the lower insulating layer on the cell region, the data storage patterns being horizontally spaced apart from each other, and the data storage patterns being connected directly to the top surfaces of the uppermost interconnection lines on the cell region.