Abstract: A process is set forth for providing a self-aligned, vertical bipolar transistor. A controlled technique is provided for providing the base and emitter features of the transistor with appropriate dimensions and properties to be useful in high frequency microwave applications. A microwave transistor is provided by this technique.

Abstract: A technique for making a microwave, high power SOI-MOFET device is set forth together with such a device. An important aspect of this structure is the presence of high conductivity metal gate fingers for the device.

Abstract: A method is set forth for forming a plurality of SOI transistors in a pattern beneath planarized reflective surfaces of a reflective display. This enables the formation of information pixels useful in devices, such as reflective LCD devices. A specific technique of providing the SOI transistors is set forth.

Abstract: A vertical double diffused metal-on-semiconductor device is produced by a method involving the formation of horizontally separated bodies of heavily doped Si and sources by a self-aligned process and a lift-off process along with the formation of trenches having negatively-sloped side-walls.

Abstract: A semiconductor device of improved ruggedness is provided which comprises a semiconductor substrate having a region of a first conductivity type on a major surface thereof; a first base region of opposite conductivity type formed selectively within said regions of first conductivity type; a second base region of opposite conductivity type formed selectively within said first base region and having a higher impurity concentration than that of said first base region; a source region of one conductivity type formed within said first and second base regions and overlying said second base region; and a polysilicon gate electrode opposed to a channel region with a gate insulating layer interposed therebetween; wherein the second base region and the source region are formed substantially entirely within the first base region; the second base region is smaller in depth than the first base region and is formed at a distance sufficiently close to the channel region to effectively reduce parasitic resistance in the firs

Abstract: A nonvolatile storage device is provided with at least one stacked poly gate structure formed on the substrate and disposed between a first trench and a second trench. The trenches each having two walls. A first doped area having a first conductivity type extending along the wall of the first trench and a second doped area having a second conductivity type extending along the wall of the second trench. The first doped area and the second doped area having heights greater than widths, the heights being parallel to the trench walls and the widths being perpendicular thereto. The trench walls are lined with a metal silicide to decrease resistivity.

Abstract: A semiconductor device of improved ruggedness is provided which comprises a semiconductor substrate having a region of a first conductivity type on a major surface thereof; a first base region of opposite conductivity type formed selectively within said regions of first conductivity type; a second base region of opposite conductivity type formed selectively within said first base region and having a higher impurity concentration than that of said first base region; a source region of one conductivity type formed within said first and second base regions and overlying said second base region; and a polysilicon gate electrode opposed to a channel region with a gate insulating layer interposed therebetween; wherein the second base region and the source region are formed substantially entirely within the first base region; the second base region is smaller in depth than the first base region and is formed at a distance sufficiently close to the channel region to effectively reduce parasitic resistance in the firs

Abstract: A multi-cellular power field effect semiconductor device includes a high conductivity layer of metal or a metal silicide disposed in intimate contact with the source region of the device. This high conductivity layer is self-aligned with respect to the aperture in the gate electrode through which the source region is diffused. The presence of this high conductivity layer allows a substantially smaller contact window to be employed for making contact between the final metallization and the source region. As a consequence, the aperture in the gate electrode and the cell size of the device can both be substantially reduced. The device has substantially improved operating characteristics. A method of producing the device is also described.

Abstract: A metal for fabricating contact structures through via openings in VLSI circuits employs a dual layer of refractory metal. A thin titanium layer is deposited, over which a molybdenum layer is formed. An annealing treatment further improves contact resistance characteristics. The method results in a contact structure which exhibits desirable properties of thermal compatibility, step coverage, contact resistance and improved processing characteristics.

Abstract: A conductive member consisting of a first conductor of an alloy of titanium and tungsten and a second conductor of a refractory metal such as molybdenum is sintered to a conductive member of silicon of low resistivity to form a low resistance contact therewith.

Abstract: Molybdenum gate electrode material is provided with an upper layer of molybdenum nitride which acts to prevent deposition of source and drain contact metal by selective chemical vapor deposition (CVD). The nitride layer also provides an improved mask for ion implantation process steps. This results in an FET structure exhibiting a high degree of planarity which is desirable for multilevel device fabrication.

Abstract: A conductive member consisting of a first conductor of an alloy of titanium and tungsten and a second conductor of a refractory metal such as molybdenum is sintered to a conductive member of silicon to a temperature in the range of 600.degree. C. to 650.degree. C. in a reducing atmosphere to form a low resistance contact.

Abstract: A layer of aluminum oxide or other insulative metal oxide is employed as an etch stop in the fabrication of very large scale integrated circuit devices. The use of such etch stops permits fabrication of unframed or borderless via openings and correspondingly permits greater metallization line pitch, smaller circuit features, and more reliable interlayer electrical contact. A method for insulative metal oxide deposition is also described.

Abstract: A capacitor structure which is particularly suitable for use in analog integrated circuit devices employs an intermediate layer of a refractory metal disposed in a thin layer overlying a flat dielectric surface. The thinness and the low reflectivity of the refractory metal facilitates precise patterning of the upper plate of the capacitor structure. In the present invention, capacitance is no longer determined by imprecise cuts through thick oxide layers or by patterning of thick metallization layers within these apertures. The use of refractory metals in the capacitor structure also readily permits the incorporation of resistive circuit elements.

Abstract: A method of forming in a silicon substrate an active region bounded by a field of silicon dioxide is described. On top of a mesa formed in the silicon substrate is provided a three layered structure including a first thin layer of silicon dioxide in contact with the top of the mesa, a second thicker layer of silicon nitride overlying the thin layer of silicon dioxide and a third layer of silicon dioxide overlying the layer of silicon nitride. A further layer of silicon nitride is formed over the three layered structure and the exposed surfaces of the silicon substrate. Spacer portions of silicon nitride are formed on the sides of the mesa and the three layered structure by anisotropically etching the fourth layer of silicon nitride. By controlling the thicknesses of the first, second and third layers, the width of the spacer portions is optimized to prevent lateral oxidation of the active region.

Abstract: The resistivity of a conductor of a refractory metal such as molybdenum is reduced by converting at least a portion of the conductor into a layer of molybdenum nitride in an atmosphere including ammonia at a temperature in the range from about 400.degree. C. to about 850.degree. C. and thereafter heating the conductor in an atmosphere including dry hydrogen in the range from about 950.degree. C. to about 1000.degree. C. for a time to convert the layer of molybdenum nitride into molybdenum and to convert molybdenum oxides in the conductor into molybdenum.

Abstract: A composite conductive structure which includes an insulating substrate on which is provided a conductor of molybdenum covered by a layer of molybdenum nitride and a method of making the structure are described. The method includes heating the conductor of molybdenum in an atmosphere of ammonia in the range from about 400.degree. C. to 850.degree. C. for a time to cause the atmosphere to react with the conductor to convert a portion of the conductor into molybdenum nitride.