Abstract: Nodes in microdevice design data are selected to form initial clusters. Typically the nodes are selected based upon the type of process to be performed on the design data. The initial clusters are then be grown, merged with other nodes, or come combination of both until the processing costs of the final clusters are compatible with the amount of resources that will be used to process the design data.

Abstract: Nodes in microdevice design data are selected to form initial clusters. Typically the nodes are selected based upon the type of process to be performed on the design data. The initial clusters are then be grown, merged with other nodes, or come combination of both until the processing costs of the final clusters are compatible with the amount of resources that will be used to process the design data.

Abstract: Nodes in microdevice design data are selected to form initial clusters. Typically the nodes are selected based upon the type of process to be performed on the design data. The initial clusters are then be grown, merged with other nodes, or come combination of both until the processing costs of the final clusters are compatible with the amount of resources that will be used to process the design data.

Abstract: Methods for improving the accuracy and performance of large complex circuit simulations including; special processing of clock structures, minimizing repetitive simulation of identical structures, partitioning designs into sub-systems for use by one of a variety of matrix inversion techniques, row partitioning matrices for parallel solving, applying two stage Newton-Ralphon's method and iteratively selecting one of a number of serial and parallel matrix solvers to perform circuit simulation.

Abstract: A fast method of estimating capacitances and wire delays in an integrated circuit design is based on placement information such as that contained in a gate schematic net list from a logic synthesis tool. A simple tree topology called a spine tree is constructed to connect the pins of the net as an approximation of actual connections therein. Capacitance is extracted for this topology assuming a worst case scenario, and Elmore delays are computed for the wire delays based on the worst-case capacitances. The method takes linear time as a function of the number of pins in the net and is much faster than using a Steiner tree method in this context.

Abstract: A system for calculating interconnect wire lateral capacitances in an automated integrated circuit design system subdivides the chip area of a circuit design to be placed and routed into a coarse grid of buckets. An estimate of congestion in each bucket is computed from an estimated amount of routing space available in the bucket and estimated consumption of routing resources by a global router. This congestion score is then used to determine the spacing of the wires in the bucket which is in turn used to estimate the capacitance of the wire segment in the bucket.