Abstract: Hair removing device (200) comprising a base member (301) having two elongate arms (302) extending outwardly while maintaining a spacing (310) in between. Two elongate flexible elements (311) form a twined section (304) between their first and second ends (303), (305) that are secured to the two arms (302). The twined section (304) is positioned in the spacing (310), under a tension. A movable member (306) extends outwardly from the base member (301) and is movable relative to the base member (301) in forward and reverse strokes. The movable member (306) urges the twined section (304) to move forward during the forward stroke and releases the twined section (304) to resiliently retract during the reverse stroke. The twined section (304) can engage and uproot hair (314) during the forward stroke.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the second doped region of the second type. A first input terminal is coupled to the first and third doped regions and a second terminal is coupled to the second doped region. At the interfaces of the doped regions are first and second depletion regions whose width can be varied by varying the voltage across the terminals from zero to full reverse bias.

Abstract: A device is presented. The device includes a substrate with a first well of a first polarity type. The first well defines a varactor region and comprises a lower first well boundary located above a bottom surface of the substrate. A second well in the varactor region is also included in the device. The second well comprises a buried well of a second polarity type having an upper second well boundary disposed below an upper portion of the first well from an upper first well boundary to the upper second well boundary and a lower second well boundary disposed above the lower first well boundary, wherein an interface of the second well and the upper portion of the first well forms a shallow PN junction in the varactor region. The device also includes a gate structure in the varactor region. The upper portion of the first well beneath the gate structure forms a channel region of the device.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (Cmax) is enhanced due to summation of two junction capacitances in parallel. At reverse bias condition, with the merging of the two junction depletion widths, the capacitor areas are drastically reduced, thereby reducing Cmin significantly.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (Cmax) is enhanced due to summation of two junction capacitances in parallel. At reverse bias condition, with the merging of the two junction depletion widths, the capacitor areas are drastically reduced, thereby reducing Cmin significantly.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (Cmax) is enhanced due to summation of two junction capacitances in parallel. At reverse bias condition, with the merging of the two junction depletion widths, the capacitor areas are drastically reduced, thereby reducing Cmin significantly.

Abstract: A device is presented. The device includes a substrate with a first well of a first polarity type. The first well defines a varactor region and comprises a lower first well boundary located above a bottom surface of the substrate. A second well in the varactor region is also included in the device. The second well comprises a buried well of a second polarity type having an upper second well boundary disposed below an upper portion of the first well from an upper first well boundary to the upper second well boundary and a lower second well boundary disposed above the lower first well boundary, wherein an interface of the second well and the upper portion of the first well forms a shallow PN junction in the varactor region. The device also includes a gate structure in the varactor region. The upper portion of the first well beneath the gate structure forms a channel region of the device.

Abstract: A MOS varactor includes a shallow PN junction beneath the surface of the substrate of a MOS structure. In depletion mode, the depletion region of the MOS structure merges with the depletion region of the shallow PN junction. This increases the total width of the depletion region of the MOS varactor to reduce Cmin.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and third doped regions are of the same type sandwiching the first doped region of the second type. A first varactor terminal is coupled to the second and third doped regions and a second varactor terminal is coupled to the first doped region. At the interfaces of the doped regions are first and second depletion regions, the widths of which can be varied by varying the voltage across the terminals from zero to full reverse bias. At zero bias condition, junction capacitance (Cmax) is enhanced due to summation of two junction capacitances in parallel. At reverse bias condition, with the merging of the two junction depletion widths, the capacitor areas are drastically reduced, thereby reducing Cmin significantly.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the second doped region of the second type. A first input terminal is coupled to the first and third doped regions and a second terminal is coupled to the second doped region. At the interfaces of the doped regions are first and second depletion regions whose width can be varied by varying the voltage across the terminals from zero to full reverse bias.

Abstract: A MOS varactor includes a shallow PN junction beneath the surface of the substrate of a MOS structure. In depletion mode, the depletion region of the MOS structure merges with the depletion region of the shallow PN junction. This increases the total width of the depletion region of the MOS varactor to reduce Cmin.

Abstract: A method for forming a thin film, electrically blowable fuse with reproducible blowing wattage using a sacrificial metal patch over a fuse dielectric layer and two etch processes; wherein the first etch process is selective to the metal patch and the second etch process is selective to the fuse dielectric layer. A fuse element, having an element width, is formed over a semiconductor structure, and a fuse dielectric layer is formed over the fuse element. A sacrificial metal patch is formed on the fuse dielectric layer; wherein the patch width being greater than the fuse element width. A second dielectric layer is formed on the sacrificial metal patch, and additional metal layers and dielectric layers may be formed over the second dielectric layer, but only the dielectric layers will remain over the fuse element.