Patents by Inventor Manjula N. Variyam

Manjula N. Variyam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7679190
    Abstract: A raised solder-mask-defined (SMD) pad configured for receiving a solder ball on a laminate electronic circuit board and a method of creating the raised SMD pad on a laminate electronic circuit board. The method may comprise forming a base bump, covering the base bump with a conductive bump layer and layering a surrounding material over an extended edge of the conductive bump layer. The surrounding material is patterned to expose a pad face and of a portion of the sides of the conductive bump layer, such that the pad face is disposed above the surface of the surrounding material. The surrounding material may be patterned by a photolithography operation or alternatively, a laser-drill operation.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: March 16, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Tz-Cheng Chiu, Manjula N Variyam
  • Patent number: 7294451
    Abstract: A raised solder-mask-defined (SMD) pad configured for receiving a solder ball on a laminate electronic circuit board and a method of creating the raised SMD pad on a laminate electronic circuit board. The method may comprise forming a base bump, covering the base bump with a conductive bump layer and layering a surrounding material over an extended edge of the conductive bump layer. The surrounding material is patterned to expose a pad face and of a portion of the sides of the conductive bump layer, such that the pad face is disposed above the surface of the surrounding material. The surrounding material may be patterned by a photolithography operation or alternatively, a laser-drill operation.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: November 13, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Tz-Cheng Chiu, Manjula N. Variyam
  • Patent number: 7085699
    Abstract: Embodiments of the present invention may provide ways and uses for correlating actual wire bonding machine adjustment parameters to inputs needed for FEA simulations in modeling actual wire bonding operations of a specified capillary design and wire bonding machine. Simulations of wire bonding operations using the specified capillary design are performed with a range of inputs (e.g., capillary displacement, wire yield strength) to develop empirical equations relating to the simulations. Actual wire bonding operations are performed using the specified capillary design with ranges of the actual wire bonding machine adjustment parameters, and the results provide empirical equations relating to the actual wire bonding machine adjustment parameters. The empirical equations are combined to provide empirical equations for the simulation inputs as functions of the actual wire bonding machine adjustment parameters. Such equations may aid in performing chip failure analysis and/or may be incorporated into design rules.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: August 1, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Manjula N. Variyam
  • Patent number: 6953707
    Abstract: According to one embodiment of the invention, a method includes providing a semiconductor chip, providing a substrate, forming a plurality of cantilevered springs outwardly from either the semiconductor chip or the substrate, engaging the cantilevered springs with respective contact pads on either the semiconductor chip or the substrate with a fixture, encapsulating the semiconductor chip and cantilevered springs with a molding, and curing the molding.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: October 11, 2005
    Assignee: Texas Instruments Incorporated
    Inventor: Manjula N. Variyam
  • Publication number: 20040241909
    Abstract: According to one embodiment of the invention, a method includes providing a semiconductor chip, providing a substrate, forming a plurality of cantilevered springs outwardly from either the semiconductor chip or the substrate, engaging the cantilevered springs with respective contact pads on either the semiconductor chip or the substrate with a fixture, encapsulating the semiconductor chip and cantilevered springs with a molding, and curing the molding.
    Type: Application
    Filed: May 28, 2003
    Publication date: December 2, 2004
    Applicant: Texas Instruments Incorporated
    Inventor: Manjula N. Variyam
  • Publication number: 20040149479
    Abstract: A plastic package for use in semiconductor devices, which has a plurality of metallic terminals exposed on a package surface and a metallic bump attached to each of said terminals. The bumps are made of reflowable metal and have approximately uniform height. An adherent layer of polymer material covers the package surface and surrounds each of the bumps to form a solid meniscus. The layer has a thickness between a quarter and one half of the bump height. An analogous methodology applies to plastic assembly boards.
    Type: Application
    Filed: January 20, 2004
    Publication date: August 5, 2004
    Inventors: Tz-Cheng Chiu, Manjula N. Variyam
  • Patent number: 6696644
    Abstract: A plastic package for use in semiconductor devices, which has a plurality of metallic terminals exposed on a package surface and a metallic bump attached to each of said terminals. The bumps are made of reflowable metal and have approximately uniform height. An adherent layer of polymer material covers the package surface and surrounds each of the bumps to form a solid meniscus. The layer has a thickness between a quarter and one half of the bump height. An analogous methodology applies to plastic assembly boards.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: February 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Tz-Cheng Chiu, Manjula N. Variyam
  • Publication number: 20040027788
    Abstract: A plastic package for use in semiconductor devices, which has a plurality of metallic terminals exposed on a package surface and a metallic bump attached to each of said terminals. The bumps are made of reflowable metal and have approximately uniform height. An adherent layer of polymer material covers the package surface and surrounds each of the bumps to form a solid meniscus. The layer has a thickness between a quarter and one half of the bump height. An analogous methodology applies to plastic assembly boards.
    Type: Application
    Filed: August 8, 2002
    Publication date: February 12, 2004
    Inventors: Tz-Cheng Chiu, Manjula N. Variyam