Patents by Inventor Manjunath Bhat

Manjunath Bhat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160092585
    Abstract: Embodiments of the disclosure are related to distribution of content in response to search signals in an enterprise environment. Embodiments of the disclosure obtain search signals from a client device associated with a user. In response to obtaining such a search signal, content stored on a resource repository can be located. Such a resource repository can be a private repository associated with an enterprise. In response to located content, a notification can be sent to the client device of the user.
    Type: Application
    Filed: November 20, 2014
    Publication date: March 31, 2016
    Inventors: Manjunath Bhat, Ramani Panchapakesan, Sivasubramaniam Sivakumar
  • Patent number: 8823846
    Abstract: Providing for pausing data readout from an optical sensor array is described herein. By way of example, an interruption period can be introduced into a readout cycle of the optical sensor array to suspend readout of data. During the interruption period, other operations related to the optical sensor array can be performed, including operations that are typically detrimental to image quality. Moreover, these operations can be performed while mitigating or avoiding negative impact on the image quality. Thus, greater flexibility is provided for global shutter operations, for instance, potentially improving frame rates and fine control of image exposure, while preserving image quality.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: September 2, 2014
    Assignee: AltaSens, Inc.
    Inventors: Laurent Blanquart, John Wallner, Manjunath Bhat
  • Publication number: 20120293699
    Abstract: Providing for pausing data readout from an optical sensor array is described herein. By way of example, an interruption period can be introduced into a readout cycle of the optical sensor array to suspend readout of data. During the interruption period, other operations related to the optical sensor array can be performed, including operations that are typically detrimental to image quality. Moreover, these operations can be performed while mitigating or avoiding negative impact on the image quality. Thus, greater flexibility is provided for global shutter operations, for instance, potentially improving frame rates and fine control of image exposure, while preserving image quality.
    Type: Application
    Filed: May 17, 2011
    Publication date: November 22, 2012
    Applicant: ALTASENS, INC.
    Inventors: Laurent Blanquart, John Wallner, Manjunath Bhat
  • Patent number: 7227384
    Abstract: A circuit for converting received domino logic signals to a static output signal includes a pair of logic gates having inputs and outputs that are cross-coupled and responsive to a domino logic input signal and a clock signal to latch the input signal during an evaluation phase defined by the clock signal. A static output is based on the latched value. One of the logic gates is tri-stateable to establish a value at the static output during a scan mode. A circuit for converting received static logic signals into domino logic signals includes a latch responsive to a clock signal to latch the value of a data signal at a predefined clock transition. A conversion circuit produces a domino logic output signal in response to the clock signal and the latched value of the data signal. A latch component is tri-stateable to establish a value at the output.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: June 5, 2007
    Assignee: Intel Corporation
    Inventors: Mondira Pant, Paul Gronowski, Randy Allmon, Manjunath Bhat, David Lin
  • Publication number: 20070035331
    Abstract: A circuit for converting received domino logic signals to a static output signal includes a pair of logic gates having inputs and outputs that are cross-coupled and responsive to a domino logic input signal and a clock signal to latch the input signal during an evaluation phase defined by the clock signal. A static output is based on the latched value. One of the logic gates is tri-stateable to establish a value at the static output during a scan mode. A circuit for converting received static logic signals into domino logic signals includes a latch responsive to a clock signal to latch the value of a data signal at a predefined clock transition. A conversion circuit produces a domino logic output signal in response to the clock signal and the latched value of the data signal. A latch component is tri-stateable to establish a value at the output.
    Type: Application
    Filed: August 11, 2005
    Publication date: February 15, 2007
    Inventors: Mondira Pant, Paul Gronowski, Randy Allmon, Manjunath Bhat, David Lin