Abstract: An automated apparatus detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are propagated up. Then, at the top-most level, lumping algorithms are employed to calculate the parasitic values for all of the top-most level nets. These values are then passed back down to the lower levels and then at each level, the layout is checked using previously computed parasitic values and EM limits. A peak current, AC-average current and AC-rms current are calculated for every layout, and then compared with the process EM rules for violations, in which the optimum line width and number of vias are specified for each interconnection.

Abstract: An automated method detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed, the parasitic (resistance and capacitance) component values extracted from a layout file are propagated up. Then, at the top-most level, lumping algorithms are employed to calculate the parasitic values for all of the top-most level nets. These values are then passed back down to the lower levels and then at each level, the layout is checked using previously computed parasitic values and EM limits. A peak current, AC-average current and AC-rms current are calculated for every layout, and then compared with the process EM rules for violations, in which the optimum line width and number of vias are specified for each interconnection.

Abstract: A method of improving the timing performance of a circuit includes the step of producing a first set of timing results from a static timing analyzer operating on a netlist that characterizes a circuit. A critical timing path within the circuit is then identified from the first set of timing results. The critical timing path is then converted into an equivalent schematic circuit representation. A simulation of the equivalent schematic circuit representation on a circuit simulator produces a second set of timing results. Timing discrepancies are then located between the first set of timing results and the second set of timing results. Based upon the timing discrepancies, cells are substituted into the critical timing path to improve the timing performance of the critical timing path.

Abstract: Disclosed is a system for automatically generating tables of buffer data which can be used during integrated circuit design to select appropriate buffers for signal distribution networks. The generated buffer data may be used by automated place and route systems to generate signal distribution networks having minimal skew. In the table, incrementally varying network features or criteria are provided (in the form of a table or list for example). Examples of such features include the length of a line connecting an L4 buffer to one or more L5 buffers and the number of L5 buffers driven by a single L4 buffer. For each incremental value of the network feature or features, one or more buffer types is specified. These buffer types have been previously modeled in the environment of the incremental value of the network features and found to meet certain criteria necessary to minimize skew.

Abstract: Disclosed is an automated method for adjusting wire lengths between connected circuit elements of an integrated circuit. The method includes the following steps: (1) receiving a value specifying a wire length that must be provided between terminals of two integrated circuit elements in the integrated circuit design; (2) defining a routing region in which the wire can be routed; and (3) automatically specifying a wire route including a serpentine section within the routing region for connecting the terminals. The serpentine section will include one or more legs sized to ensure that the wire route has the specified wire length. Specifically disclosed is the application of this method to size wiring between two clock buffers in separate and adjacent stages of a clock distribution network. The two clock buffers may be provided in third and fourth stages of the clock distribution network.