Abstract: An apparatus to facilitate thread synchronization is disclosed. The apparatus comprises one or more processors to execute a producer thread to generate a plurality of commands, execute a consumer thread to process the plurality of commands and synchronize the producer thread with the consumer thread, including updating a producer fence value upon generation of in-order commands, updating a consumer fence value upon processing of the in-order commands and performing a synchronization operation based on the consumer fence value, wherein the producer fence value and the consumer fence value each correspond to an order position of an in-order command.

Abstract: A computer system may comprise a processor, a chipset, and a memory. The processor may enter low-power mode based on the occurrence of pre-specified events. A graphics controller of the chipset may drive the display such as the LVDS display panel to a self-refresh mode and then enter low-power mode. The display may refresh the pixels with the data persevered prior to entering the self-refresh mode. The memory and a memory controller of the chipset may also enter low-power mode. The graphics controller may enter normal mode after the processor enters the normal mode and may pull back the display to the normal mode.