Patents by Inventor Manjunath Haritsa

Manjunath Haritsa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for topology based noise estimation of submicron integrated circuit designs
    Patent number: 6665845
    Abstract: A tool for computing noise coupled onto victim lines from aggressor lines of an integrated circuit has code for traversing a victim line of the integrated circuit layout to measure its length, its average width, a coupling length, and a harmonic mean of spacing between the victim line and aggressor lines. The tool has code for computing a resistance, estimated coupling capacitance, and total capacitance of the victim line from these parameters.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: December 16, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Kathirqamar Aingaran, Stephan Hoerold, Manjunath Haritsa, Farn Wang