Patents by Inventor Manjunath Kudlur
Manjunath Kudlur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230410389Abstract: A method for applying a style to an input image to generate a stylized image. The method includes maintaining data specifying respective parameter values for each image style in a set of image styles, receiving an input including an input image and data identifying an input style to be applied to the input image to generate a stylized image that is in the input style, determining, from the maintained data, parameter values for the input style, and generating the stylized image by processing the input image using a style transfer neural network that is configured to process the input image to generate the stylized image.Type: ApplicationFiled: September 6, 2023Publication date: December 21, 2023Inventors: Jonathon Shlens, Vincent Dumoulin, Manjunath Kudlur Venkatakrishna
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Patent number: 11776167Abstract: A method for applying a style to an input image to generate a stylized image. The method includes maintaining data specifying respective parameter values for each image style in a set of image styles, receiving an input including an input image and data identifying an input style to be applied to the input image to generate a stylized image that is in the input style, determining, from the maintained data, parameter values for the input style, and generating the stylized image by processing the input image using a style transfer neural network that is configured to process the input image to generate the stylized image.Type: GrantFiled: November 12, 2019Date of Patent: October 3, 2023Assignee: Google LLCInventors: Jonathon Shlens, Vincent Dumoulin, Manjunath Kudlur Venkatakrishna
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Publication number: 20210295161Abstract: Systems and Methods for training a neural network represented as a computational graph are disclosed. An example method begins with obtaining data representing a computational graph. The computational graph is then augmented to generate a training computational graph for training the neural network using a machine learning training algorithm that includes computing a gradient of an objective function with respect to each of the parameters of the neural network. Augmenting the computational graph includes inserting a plurality of gradient nodes and training edges into the computational graph to generate a backward path through the computational graph that represents operations for computing the gradients of the objective function with respect to the parameters of the neural network. The neural network is trained using the machine learning training algorithm by executing the training computational graph.Type: ApplicationFiled: April 2, 2021Publication date: September 23, 2021Inventors: Yuan Yu, Manjunath Kudlur Venkatakrishna
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Patent number: 10970628Abstract: Systems and Methods for training a neural network represented as a computational graph are disclosed. An example method begins with obtaining data representing a computational graph. The computational graph is then augmented to generate a training computational graph for training the neural network using a machine learning training algorithm that includes computing a gradient of an objective function with respect to each of the parameters of the neural network. Augmenting the computational graph includes inserting a plurality of gradient nodes and training edges into the computational graph to generate a backward path through the computational graph that represents operations for computing the gradients of the objective function with respect to the parameters of the neural network. The neural network is trained using the machine learning training algorithm by executing the training computational graph.Type: GrantFiled: November 9, 2016Date of Patent: April 6, 2021Assignee: Google LLCInventors: Yuan Yu, Manjunath Kudlur Venkatakrishna
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Publication number: 20200082578Abstract: A method for applying a style to an input image to generate a stylized image. The method includes maintaining data specifying respective parameter values for each image style in a set of image styles, receiving an input including an input image and data identifying an input style to be applied to the input image to generate a stylized image that is in the input style, determining, from the maintained data, parameter values for the input style, and generating the stylized image by processing the input image using a style transfer neural network that is configured to process the input image to generate the stylized image.Type: ApplicationFiled: November 12, 2019Publication date: March 12, 2020Inventors: Jonathon Shlens, Vincent Dumoulin, Manjunath Kudlur Venkatakrishna
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Patent number: 10535164Abstract: A method for applying a style to an input image to generate a stylized image. The method includes maintaining data specifying respective parameter values for each image style in a set of image styles, receiving an input including an input image and data identifying an input style to be applied to the input image to generate a stylized image that is in the input style, determining, from the maintained data, parameter values for the input style, and generating the stylized image by processing the input image using a style transfer neural network that is configured to process the input image to generate the stylized image.Type: GrantFiled: April 10, 2019Date of Patent: January 14, 2020Assignee: Google Inc.Inventors: Jonathon Shlens, Vincent Dumoulin, Manjunath Kudlur Venkatakrishna
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Publication number: 20190236814Abstract: A method for applying a style to an input image to generate a stylized image. The method includes maintaining data specifying respective parameter values for each image style in a set of image styles, receiving an input including an input image and data identifying an input style to be applied to the input image to generate a stylized image that is in the input style, determining, from the maintained data, parameter values for the input style, and generating the stylized image by processing the input image using a style transfer neural network that is configured to process the input image to generate the stylized image.Type: ApplicationFiled: April 10, 2019Publication date: August 1, 2019Inventors: Jonathon Shlens, Vincent Dumoulin, Manjunath Kudlur Venkatakrishna
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Publication number: 20170132513Abstract: Systems and Methods for training a neural network represented as a computational graph are disclosed. An example method begins with obtaining data representing a computational graph. The computational graph is then augmented to generate a training computational graph for training the neural network using a machine learning training algorithm that includes computing a gradient of an objective function with respect to each of the parameters of the neural network. Augmenting the computational graph includes inserting a plurality of gradient nodes and training edges into the computational graph to generate a backward path through the computational graph that represents operations for computing the gradients of the objective function with respect to the parameters of the neural network. The neural network is trained using the machine learning training algorithm by executing the training computational graph.Type: ApplicationFiled: November 9, 2016Publication date: May 11, 2017Inventors: Yuan Yu, Manjunath Kudlur Venkatakrishna
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Patent number: 9639336Abstract: One embodiment of the present invention sets forth a technique for reducing the number of assembly instructions included in a computer program. The technique involves receiving a directed acyclic graph (DAG) that includes a plurality of nodes, where each node includes an assembly instruction of the computer program, hierarchically parsing the plurality of nodes to identify at least two assembly instructions that are vectorizable and can be replaced by a single vectorized assembly instruction, and replacing the at least two assembly instructions with the single vectorized assembly instruction.Type: GrantFiled: October 25, 2012Date of Patent: May 2, 2017Assignee: NVIDIA CorporationInventors: Vinod Grover, Manjunath Kudlur, Michael Murphy
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Patent number: 9134979Abstract: A basic block within a thread program is characterized for convergence based on mapping the basic block to an indicator subnet within a corresponding Petri net generated to model the thread program. Each block within the thread program may be similarly characterized. Each corresponding Petri net is enumerated to generate a corresponding state space graph. If the state space graph includes an exit node with an odd execution count attribute, such as by Petri net coloring, then the corresponding basic block is divergent. The corresponding basic block is convergent otherwise. Using this characterization technique, a thread program compiler may advantageously identify all convergent blocks within a thread program and apply appropriate optimizations to the convergent blocks.Type: GrantFiled: February 6, 2013Date of Patent: September 15, 2015Assignee: NVIDIA CorporationInventor: Manjunath Kudlur
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Method and system for heterogeneous filtering framework for shared memory data access hazard reports
Patent number: 9038080Abstract: A system and method for detecting, filtering, prioritizing and reporting shared memory hazards are disclosed. The method includes, for a unit of hardware operating on a block of threads, mapping a plurality of shared memory locations assigned to the unit to a tracking table. The tracking table comprises initialization information for each shared memory location. The method also includes, for an instruction of a program within a barrier region, identifying a potential conflict by identifying a second access to a location in shared memory within a block of threads executed by the hardware unit. First information associated with a first access and second information associated with the second access to the location is determined. Filter criteria is applied to the first and second information to determine whether the instruction causes a reportable hazard. The instruction is reported when it causes the reportable hazard.Type: GrantFiled: December 27, 2012Date of Patent: May 19, 2015Assignee: NVIDIA CORPORATIONInventors: Vyas Venkataraman, Manjunath Kudlur, Vinod Grover -
Publication number: 20140223420Abstract: A basic block within a thread program is characterized for convergence based on mapping the basic block to an indicator subnet within a corresponding Petri net generated to model the thread program. Each block within the thread program may be similarly characterized. Each corresponding Petri net is enumerated to generate a corresponding state space graph. If the state space graph includes an exit node with an odd execution count attribute, such as by Petri net coloring, then the corresponding basic block is divergent. The corresponding basic block is convergent otherwise. Using this characterization technique, a thread program compiler may advantageously identify all convergent blocks within a thread program and apply appropriate optimizations to the convergent blocks.Type: ApplicationFiled: February 6, 2013Publication date: August 7, 2014Applicant: NVIDIA CORPORATIONInventor: Manjunath Kudlur
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Publication number: 20140149480Abstract: A system, method, and computer program product are provided for transposing a matrix. In use, a matrix is identified. Additionally, the matrix is transposed utilizing row-wise operations and column-wise operations, where the row-wise operations and the column-wise operations are performed independently.Type: ApplicationFiled: October 24, 2013Publication date: May 29, 2014Applicant: NVIDIA CorporationInventors: Bryan Christopher Catanzaro, Manjunath Kudlur
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Publication number: 20140143755Abstract: A system and method are provided for inserting synchronization statements into a program file to mitigate race conditions. The method includes reading a program file and determining one or more convergent statements in the program file. The method also includes inserting one or more synchronization statements in the program file between the determined convergent statements. The method further includes removing one or more of the inserted synchronization statements and writing the modified program file. The method may include, after removing the inserted synchronization statements, identifying to a user any remaining inserted synchronization statements.Type: ApplicationFiled: November 20, 2012Publication date: May 22, 2014Applicant: Nvidia CorporationInventors: Vinod Grover, Xiangyun Kong, Jae-Woo Lee, Manjunath Kudlur, Jian-Zhong Wang
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METHOD AND SYSTEM FOR HETEROGENEOUS FILTERING FRAMEWORK FOR SHARED MEMORY DATA ACCESS HAZARD REPORTS
Publication number: 20130305252Abstract: A system and method for detecting, filtering, prioritizing and reporting shared memory hazards are disclosed. The method includes, for a unit of hardware operating on a block of threads, mapping a plurality of shared memory locations assigned to the unit to a tracking table. The tracking table comprises initialization information for each shared memory location. The method also includes, for an instruction of a program within a barrier region, identifying a potential conflict by identifying a second access to a location in shared memory within a block of threads executed by the hardware unit. First information associated with a first access and second information associated with the second access to the location is determined. Filter criteria is applied to the first and second information to determine whether the instruction causes a reportable hazard. The instruction is reported when it causes the reportable hazard.Type: ApplicationFiled: December 27, 2012Publication date: November 14, 2013Applicant: NVIDIA CORPORATIONInventors: Vyas Venkataraman, Manjunath Kudlur, Vinod Grover -
Publication number: 20130304996Abstract: A system and method for detecting shared memory hazards are disclosed. The method includes, for a unit of hardware operating on a block of threads, mapping a plurality of shared memory locations assigned to the unit to a tracking table. The tracking table comprises an initialization bit as well as access type information, collectively called the state tracking bits for each shared memory location. The method also includes, for an instruction of a program within a barrier region, identifying a second access to a location in shared memory within a block of threads executed by the hardware unit. The second access is identified based on a status of the state tracking bits. The method also includes determining a hazard based on a first type of access and a second type of access to the shared memory location. Information related to the first access is provided in the table.Type: ApplicationFiled: December 27, 2012Publication date: November 14, 2013Applicant: NVIDIA CorporationInventors: Vyas Venkataraman, Jaydeep Marathe, Manjunath Kudlur, Vinod Grover, Geoffrey Gerfin, Alban Douillet, Mayank Kaushik