Patents by Inventor Manjunatha Gowda

Manjunatha Gowda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Deep learning based identification of difficult to test nodes
    Patent number: 11574097
    Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: February 7, 2023
    Assignee: NVIDIA CORP.
    Inventors: Harbinder Sikka, Kaushik Narayanun, Lijuan Luo, Karthikeyan Natarajan, Manjunatha Gowda, Sandeep Gangundi
  • DEEP LEARNING BASED IDENTIFICATION OF DIFFICULT TO TEST NODES
    Publication number: 20210295169
    Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
    Type: Application
    Filed: April 15, 2021
    Publication date: September 23, 2021
    Applicant: NVIDIA Corp.
    Inventors: Harbinder Sikka, Kaushik Narayanun, Lijuan Luo, Karthikeyan Natarajan, Manjunatha Gowda, Sandeep Gangundi
  • Deep learning based identification of difficult to test nodes
    Patent number: 11010516
    Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: May 18, 2021
    Assignee: NVIDIA Corp.
    Inventors: Harbinder Sikka, Kaushik Narayanun, Lijuan Luo, Karthikeyan Natarajan, Manjunatha Gowda, Sandeep Gangundi
  • DEEP LEARNING BASED IDENTIFICATION OF DIFFICULT TO TEST NODES
    Publication number: 20200151289
    Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
    Type: Application
    Filed: August 9, 2019
    Publication date: May 14, 2020
    Applicant: NVIDIA Corp.
    Inventors: Harbinder Sikka, Kaushik Narayanun, Lijuan Luo, Karthikeyan Natarajan, Manjunatha Gowda, Sandeep Gangundi
  • Closed-loop adaptive voltage scaling for integrated circuits
    Patent number: 9158319
    Abstract: In one embodiment, an integrated circuit (IC) device includes a first logic block having performance characteristics, a first critical path monitor (CPM) configured to monitor the performance characteristics of the first logic block, and a first CPM envelope circuit enveloping the first CPM. The first logic block is configured to operate in at least one of a first functional mode and a first scan mode. The first CPM is adapted to operate in at least one of a second functional mode and a second scan mode. The first and second functional modes use higher clock frequencies, respectively, than the first and second scan modes. The first CPM envelope circuit comprises a clock-gate circuit adapted to allow the IC device to operate in a mixed mode, wherein the first CPM operates in the second functional mode while the first logic block operates in the first scan mode.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: October 13, 2015
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Manjunatha Gowda, Ramnath Venkatraman, Thai M. Nguyen, Hai H. Tan, Prasad Subbarao
  • CLOSED-LOOP ADAPTIVE VOLTAGE SCALING FOR INTEGRATED CIRCUITS
    Publication number: 20150109052
    Abstract: In one embodiment, an integrated circuit (IC) device includes a first logic block having performance characteristics, a first critical path monitor (CPM) configured to monitor the performance characteristics of the first logic block, and a first CPM envelope circuit enveloping the first CPM. The first logic block is configured to operate in at least one of a first functional mode and a first scan mode. The first CPM is adapted to operate in at least one of a second functional mode and a second scan mode. The first and second functional modes use higher clock frequencies, respectively, than the first and second scan modes. The first CPM envelope circuit comprises a clock-gate circuit adapted to allow the IC device to operate in a mixed mode, wherein the first CPM operates in the second functional mode while the first logic block operates in the first scan mode.
    Type: Application
    Filed: November 25, 2013
    Publication date: April 23, 2015
    Applicant: LSI Corporation
    Inventors: Manjunatha Gowda, Ramnath Venkatraman, Thai M. Nguyen, Hai H. Tan, Prasad Subbarao
  • Distributed delay prediction of multi-million gate deep sub-micron ASIC designs
    Patent number: 7006962
    Abstract: A method and system for predicting delay of a multi-million gate sub-micron ASIC design is disclosed. The method and system include automatically partitioning a netlist into at least two logic cones, and running respective instances of a delay prediction application on the logic cones on at least two computers in parallel.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: February 28, 2006
    Assignee: LSI Logic Corporation
    Inventors: Saket Goyal, Santhanakrishnan Raman, Prabhakaran Krishnamurthy, Prasad Subbarao, Manjunatha Gowda