Abstract: An integrated circuit (IC) device includes a die including a silicon region having a coefficient of thermal expansion (CTEsilicon), and a conductive contact on a first side of the first die. An encapsulant laterally adjacent the silicon region of the first die has a coefficient of thermal expansion (CTEencapsulant), wherein a mismatch between the CTEsilicon and the CTEencapsulant defines a thermal stress interface between the silicon region and the encapsulant. The IC device includes a dielectric layer formed over the first die and the encapsulant, and includes a dielectric spacer region extending over and laterally across the thermal stress interface. The IC device includes a redistribution layer (RDL) including an RDL element formed over the dielectric spacer region and electrically connected to the conductive contact through an opening in the dielectric layer, wherein the RDL element is physically spaced apart from the thermal stress interface by the dielectric spacer region.

Abstract: An apparatus includes a pair of substrates with conductive material formed on portions of inwardly facing surfaces thereof, and a step formed in or on the conductive material on one of the pair of substrates. A lead frame having leads and electronic components having different respective thicknesses are mounted between the conductive materials on the pair of substrates. The step has a step thickness dimensioned to facilitate electrical contact between a thickest one of the electronic components or the leads with the step in the conductive material on one of the pair of substrates and the conductive material on the one other of the pair of substrates. An electrical signal path is formed between the electronic components or the leads disposed in electrical contact with the step and the conductive material on the one other of the pair of substrates.

Abstract: An integrated circuit (IC) device includes a die including a silicon region having a coefficient of thermal expansion (CTEsilicon), and a conductive contact on a first side of the first die. An encapsulant laterally adjacent the silicon region of the first die has a coefficient of thermal expansion (CTEencapsulant), wherein a mismatch between the CTEsilicon and the CTEencapsulant defines a thermal stress interface between the silicon region and the encapsulant. The IC device includes a dielectric layer formed over the first die and the encapsulant, and includes a dielectric spacer region extending over and laterally across the thermal stress interface. The IC device includes a redistribution layer (RDL) including an RDL element formed over the dielectric spacer region and electrically connected to the conductive contact through an opening in the dielectric layer, wherein the RDL element is physically spaced apart from the thermal stress interface by the dielectric spacer region.

Abstract: An apparatus includes first electrical components, wherein a respective first electrical component has first connection areas, and second electrical components, wherein a respective second electrical component has second connection areas. The apparatus also includes support structures, wherein a respective support structure is mounted to a respective first electrical component to limit a lateral range of movement of a respective second electrical component relative to the respective first electrical component. The apparatus further includes masses of connection material to at least partially connect corresponding ones of the first connection areas of the first electrical components and the second connection areas of the second electrical components.

Abstract: A method comprising: molding a structural support coating over the gate pad and source pad at the front side of a wafer; back-side processing the wafer to remove a portion of a silicon layer so that the silicon layer has a post-process thickness, wherein the post-process thickness is less than the pre-process thickness; and removing the structural support coating at the front side of the wafer sufficiently to expose the gate pad and source pad. An electronic device comprising: a silicon layer less than 50 ?m thick and defining a back side of the electronic device, a metal layer on the silicon layer, wherein the metal layer defines a front side of the electronic device, wherein the metal layer has a source pad and a gate pad; and a structural support coating between the source pad and the gate pad.

Abstract: Electronic packages comprising: a die with a bond pad, a mold compound encapsulating at least exposed surfaces of the die surrounding the bond pad, and a unitary redistribution layer plate on at least a portion of the mold compound and extending through the mold compound in electrical communication with the bond pad. A method comprising: depositing a plug on a die bond pad, encapsulating a proximal end of the plug and at least a portion of the die proximate the proximal end of the plug with a mold compound, removing the plug from the bond pad to form an opening in the mold compound, and depositing a redistribution layer plate on the mold compound and in the opening in the mold compound on the bond pad.

Abstract: A method of packaging a semiconductor device having a bond pad on a surface thereof includes forming a redistribution material electrically coupled to the bond pad, forming a dielectric material over the redistribution material, and removing a first portion of the dielectric material to expose a first portion of the redistribution material. Semiconductor packages may include a redistribution layer having a first portion adjacent and coupled to a first contact of the package, a second portion exposed by a first opening in a dielectric material, and a redistribution line electrically coupled to a first bond pad, the first portion, and the second portion. Such a package may be tested placing at least one probe needle in contact with at least one terminal of the package, providing a test signal from the probe needle to the package through the terminal, and detecting signals using the needle.

Abstract: A method of packaging a semiconductor device having a bond pad on a surface thereof includes forming a redistribution material electrically coupled to the bond pad, forming a dielectric material over the redistribution material, and removing a first portion of the dielectric material to expose a first portion of the redistribution material. Semiconductor packages may include a redistribution layer having a first portion adjacent and coupled to a first contact of the package, a second portion exposed by a first opening in a dielectric material, and a redistribution line electrically coupled to a first bond pad, the first portion, and the second portion. Such a package may be tested placing at least one probe needle in contact with at least one terminal of the package, providing a test signal from the probe needle to the package through the terminal, and detecting signals using the needle.