Patents by Inventor Mann-Ho Cho

Mann-Ho Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071757
    Abstract: A method of manufacturing a stacked structure includes forming a first metal buffer layer including crystal grains on a base substrate, forming a second metal buffer material layer on the first metal buffer layer, and crystallizing the second metal buffer material layer to form a second metal buffer layer, wherein the second metal buffer material layer includes crystal grains, and a density of the crystal grains of the second metal buffer material layer is lower than a density of the crystal grains of the first metal buffer layer.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicants: Samsung Display Co., LTD., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Mann Ho CHO, Kwang Sik JEONG, Hyeon Sik KIM, Hyun Eok SHIN, Byung Soo SO, Ju Hyun LEE
  • Patent number: 11837468
    Abstract: A method of manufacturing a stacked structure includes forming a first metal buffer layer including crystal grains on a base substrate, forming a second metal buffer material layer on the first metal buffer layer, and crystallizing the second metal buffer material layer to form a second metal buffer layer, wherein the second metal buffer material layer includes crystal grains, and a density of the crystal grains of the second metal buffer material layer is lower than a density of the crystal grains of the first metal buffer layer.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: December 5, 2023
    Assignees: SAMSUNG DISPLAY CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Mann Ho Cho, Kwang Sik Jeong, Hyeon Sik Kim, Hyun Eok Shin, Byung Soo So, Ju Hyun Lee
  • Publication number: 20230274948
    Abstract: A method of fabricating a semiconductor device includes forming a semiconductor layer, the semiconductor layer including a two-dimensional semiconductor material, forming a sacrificial layer on the semiconductor layer, forming a metal contact layer on the sacrificial layer, and removing the sacrificial layer. After the sacrificial layer is removed, the semiconductor layer and the metal contact layer are bonded to each other through a van der Waals bond.
    Type: Application
    Filed: October 18, 2022
    Publication date: August 31, 2023
    Applicants: Samsung Electronics Co., Ltd., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Mann Ho CHO, Gi Hyeon KWON
  • Publication number: 20220130667
    Abstract: A method of manufacturing a stacked structure includes forming a first metal buffer layer including crystal grains on a base substrate, forming a second metal buffer material layer on the first metal buffer layer, and crystallizing the second metal buffer material layer to form a second metal buffer layer, wherein the second metal buffer material layer includes crystal grains, and a density of the crystal grains of the second metal buffer material layer is lower than a density of the crystal grains of the first metal buffer layer.
    Type: Application
    Filed: September 8, 2021
    Publication date: April 28, 2022
    Applicants: Samsung Display Co., LTD., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Mann Ho CHO, Kwang Sik JEONG, Hyeon Sik KIM, Hyun Eok SHIN, Byung Soo SO, Ju Hyun LEE
  • Patent number: 10886451
    Abstract: Provided are a thermoelectric material, a method of fabricating the same, and a thermoelectric device. The thermoelectric material includes a first material layer including a chalcogen element; and a second material layer including a reaction compound between the chalcogen element and a metal element, wherein the thermoelectric material has a structure in which the first material layer is inserted in the second material layer.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: January 5, 2021
    Assignee: UNIVERSITY-INDUSTRY FOUNDATION (UIF), YONSEI UNIVERSITY
    Inventors: Mann Ho Cho, Hye Jin Choi, Ji Min Chae, Han Bum Park
  • Patent number: 10776549
    Abstract: A method for manufacturing a semiconductor device with an improved doping profile is provided. The method includes providing a measuring target including a first region having a plurality of layers, inputting a first input signal into the measuring target and measuring a resulting first output signal, such as a change over time of a first output electric field that is transmitted through or reflected by the first region. Based on a first model including first structural information of a plurality of first modeling layers and information on doping concentrations of each of the plurality of first modeling layers, calculating a second output signal. When a result of comparing the first output signal with the second output signal is smaller than a threshold value, a three-dimensional model of the measuring target may be estimated based on the first model.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: September 15, 2020
    Assignees: SAMSUNG ELECTRONICS CO., LTD., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Dong Chan Suh, Mann-Ho Cho, Woo Bin Song, Kwang Sik Jeong
  • Publication number: 20190370429
    Abstract: A method for manufacturing a semiconductor device with an improved doping profile is provided. The method includes providing a measuring target including a first region having a plurality of layers, inputting a first input signal into the measuring target and measuring a resulting first output signal, such as a change over time of a first output electric field that is transmitted through or reflected by the first region. Based on a first model including first structural information of a plurality of first modeling layers and information on doping concentrations of each of the plurality of first modeling layers, calculating a second output signal. When a result of comparing the first output signal with the second output signal is smaller than a threshold value, a three-dimensional model of the measuring target may be estimated based on the first model.
    Type: Application
    Filed: February 4, 2019
    Publication date: December 5, 2019
    Inventors: Dong Chan SUH, Mann-Ho CHO, Woo Bin SONG, Kwang Sik JEONG
  • Publication number: 20190035995
    Abstract: Provided are a thermoelectric material, a method of fabricating the same, and a thermoelectric device. The thermoelectric material includes a first material layer including a chalcogen element; and a second material layer including a reaction compound between the chalcogen element and a metal element, wherein the thermoelectric material has a structure in which the first material layer is inserted in the second material layer.
    Type: Application
    Filed: March 9, 2017
    Publication date: January 31, 2019
    Inventors: Mann Ho Cho, Hye Jin Choi, Ji Min Chae, Han Bum Park
  • Patent number: 9070478
    Abstract: A variable resistive memory device includes an array of a plurality of memory cells. Each of the plurality of memory cells includes first and second electrodes, and an SbmSen material layer (where m and n are positive numbers, respectively) interposed between the first electrode and the second electrode. The SbmSen material layer includes a separation structure in which a plurality of Sb atoms are in contact with a plurality of Se atoms.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: June 30, 2015
    Assignees: Hynix Semiconductor Inc., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Mann Ho Cho, Ju Heyuck Baeck, Tae Hyeon Kim, Hye Jin Choi
  • Publication number: 20130141967
    Abstract: A variable resistive memory device includes an array of a plurality of memory cells. Each of the plurality of memory cells includes first and second electrodes, and an SbmSen material layer (where m and n are positive numbers, respectively) interposed between the first electrode and the second electrode. The SbmSen material layer includes a separation structure in which a plurality of Sb atoms are in contact with a plurality of Se atoms.
    Type: Application
    Filed: May 30, 2012
    Publication date: June 6, 2013
    Inventors: Mann Ho CHO, Ju Heyuck Baeck, Tae Hyeon Kim, Hye Jin Choi
  • Patent number: 8420551
    Abstract: Example methods and example embodiments include methods of fabricating semiconductor devices and semiconductor devices fabricated by the same. Example fabricating methods include forming a first nanowire, oxidizing the first nanowire to form a first nanostructure including a first insulator and a second nanowire, and oxidizing the second nanowire to form a second nanostructure including a second insulator and nanodots. Example semiconductor devices include nanostructures including nanodots and nanostructures providing storage nodes in memory devices.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: April 16, 2013
    Assignees: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation
    Inventors: Myung-Jong Kim, In-Seok Yeo, Dae-Hong Ko, Hyun-Chul Sohn, Mann-Ho Cho, Sang-Yeon Kim
  • Publication number: 20110284815
    Abstract: A memory device includes a substrate and a memory cell including a first electrode on the substrate, a phase-change material region on the first electrode and a second electrode on the phase-change material region opposite the first electrode. The memory device further includes a stress relief buffer adjacent a sidewall of the phase-change material region between the first and second electrodes. In some embodiments, the stress relief buffer includes a stress relief region contacting the sidewall of the phase-change material region. In further embodiments, the stress relief buffer includes a void adjacent the sidewall of the phase-change material region.
    Type: Application
    Filed: March 24, 2011
    Publication date: November 24, 2011
    Inventors: Ik-soo Kim, Soon-oh Park, Dong-ho Ahn, Sung-lae Cho, Dae-hong Ko, Hyun-chul Sohn, Ki-hoon Do, Mann-ho Cho
  • Publication number: 20110165761
    Abstract: Example methods and example embodiments include methods of fabricating semiconductor devices and semiconductor devices fabricated by the same. Example fabricating methods include forming a first nanowire, oxidizing the first nanowire to form a first nanostructure including a first insulator and a second nanowire, and oxidizing the second nanowire to form a second nanostructure including a second insulator and nanodots. Example semiconductor devices include nanostructures including nanodots and nanostructures providing storage nodes in memory devices.
    Type: Application
    Filed: December 6, 2010
    Publication date: July 7, 2011
    Inventors: Myung-Jong KIM, In-Seok Yeo, Dae-Hong Ko, Hyun-Chul Sohn, Mann-Ho Cho, Sang-Yeon Kim