Patents by Inventor Mann-Ho Cho

Mann-Ho Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10776549
    Abstract: A method for manufacturing a semiconductor device with an improved doping profile is provided. The method includes providing a measuring target including a first region having a plurality of layers, inputting a first input signal into the measuring target and measuring a resulting first output signal, such as a change over time of a first output electric field that is transmitted through or reflected by the first region. Based on a first model including first structural information of a plurality of first modeling layers and information on doping concentrations of each of the plurality of first modeling layers, calculating a second output signal. When a result of comparing the first output signal with the second output signal is smaller than a threshold value, a three-dimensional model of the measuring target may be estimated based on the first model.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: September 15, 2020
    Assignees: SAMSUNG ELECTRONICS CO., LTD., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Dong Chan Suh, Mann-Ho Cho, Woo Bin Song, Kwang Sik Jeong
  • Publication number: 20190370429
    Abstract: A method for manufacturing a semiconductor device with an improved doping profile is provided. The method includes providing a measuring target including a first region having a plurality of layers, inputting a first input signal into the measuring target and measuring a resulting first output signal, such as a change over time of a first output electric field that is transmitted through or reflected by the first region. Based on a first model including first structural information of a plurality of first modeling layers and information on doping concentrations of each of the plurality of first modeling layers, calculating a second output signal. When a result of comparing the first output signal with the second output signal is smaller than a threshold value, a three-dimensional model of the measuring target may be estimated based on the first model.
    Type: Application
    Filed: February 4, 2019
    Publication date: December 5, 2019
    Inventors: Dong Chan SUH, Mann-Ho CHO, Woo Bin SONG, Kwang Sik JEONG
  • Patent number: 8420551
    Abstract: Example methods and example embodiments include methods of fabricating semiconductor devices and semiconductor devices fabricated by the same. Example fabricating methods include forming a first nanowire, oxidizing the first nanowire to form a first nanostructure including a first insulator and a second nanowire, and oxidizing the second nanowire to form a second nanostructure including a second insulator and nanodots. Example semiconductor devices include nanostructures including nanodots and nanostructures providing storage nodes in memory devices.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: April 16, 2013
    Assignees: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation
    Inventors: Myung-Jong Kim, In-Seok Yeo, Dae-Hong Ko, Hyun-Chul Sohn, Mann-Ho Cho, Sang-Yeon Kim
  • Publication number: 20110284815
    Abstract: A memory device includes a substrate and a memory cell including a first electrode on the substrate, a phase-change material region on the first electrode and a second electrode on the phase-change material region opposite the first electrode. The memory device further includes a stress relief buffer adjacent a sidewall of the phase-change material region between the first and second electrodes. In some embodiments, the stress relief buffer includes a stress relief region contacting the sidewall of the phase-change material region. In further embodiments, the stress relief buffer includes a void adjacent the sidewall of the phase-change material region.
    Type: Application
    Filed: March 24, 2011
    Publication date: November 24, 2011
    Inventors: Ik-soo Kim, Soon-oh Park, Dong-ho Ahn, Sung-lae Cho, Dae-hong Ko, Hyun-chul Sohn, Ki-hoon Do, Mann-ho Cho
  • Publication number: 20110165761
    Abstract: Example methods and example embodiments include methods of fabricating semiconductor devices and semiconductor devices fabricated by the same. Example fabricating methods include forming a first nanowire, oxidizing the first nanowire to form a first nanostructure including a first insulator and a second nanowire, and oxidizing the second nanowire to form a second nanostructure including a second insulator and nanodots. Example semiconductor devices include nanostructures including nanodots and nanostructures providing storage nodes in memory devices.
    Type: Application
    Filed: December 6, 2010
    Publication date: July 7, 2011
    Inventors: Myung-Jong KIM, In-Seok Yeo, Dae-Hong Ko, Hyun-Chul Sohn, Mann-Ho Cho, Sang-Yeon Kim