Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.

Abstract: A masking and etching technique during the formation of a memory cell capacitor which simultaneously separates storage poly into individual storage poly nodes and etches recesses into the storage poly nodes which increase the surface area of the storage poly nodes and thereby increase the capacitance of a completed memory cell without additional processing steps.

Abstract: A masking and etching technique during the formation of a memory cell capacitor which simultaneously separates storage poly into individual storage poly nodes and etches recesses into the storage poly nodes which increase the surface area of the storage poly nodes and thereby increase the capacitance of a completed memory cell without additional processing steps.

Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.

Abstract: A method for upgrading or remediating semiconductor devices utilizing a remediation, adaptation, modification or upgrade chip in a piggyback configuration with a primary bare chip to achieve an upgrade, modification or adaptation of the primary chip or remedy a design or fabrication problem with the primary chip.

Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.

Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.

Abstract: A test socket for testing a packaged semiconductor device. The test socket includes a test substrate, at least one support member, and at least one securing member. Terminals of the test substrate are electrically connectable to a testing device. The terminals may by located within recesses that are configured to receive leads. The shapes of each support member and securing member may be complementary to the respective shapes of the bottom and top surfaces of leads extending from the packaged semiconductor device. Upon placement of a packaged semiconductor device on the test substrate, the leads are aligned with and positioned against their corresponding terminals and the support member. The securing elements are then placed against the leads to bias each lead against its corresponding terminal.

Abstract: A test socket for testing a packaged semiconductor device. The test socket includes a test substrate, at least one support member, and at least one securing member. Terminals of the test substrate are electrically connectable to a testing device. The terminals may by located within recesses that are configured to receive leads. The shapes of each support member and securing member may be complementary to the respective shapes of the bottom and top surfaces of leads extending from the packaged semiconductor device. Upon placement of a packaged semiconductor device on the test substrate, the leads are aligned with and positioned against their corresponding terminals and the support member. The securing elements are then placed against the leads to bias each lead against its corresponding terminal.

Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.

Abstract: A test socket for testing a packaged semiconductor device. The test socket includes a test substrate, at least one support member, and at least one securing member. Terminals of the test substrate are electrically connectable to a testing device. The terminals may by located within recesses that are configured to receive leads. The shapes of each support member and securing member may be complementary to the respective shapes of the bottom and top surfaces of leads extending from the packaged semiconductor device. Upon placement of a packaged semiconductor device on the test substrate, the leads are aligned with and positioned against their corresponding terminals and the support member. The securing elements are then placed against the leads to bias each lead against its corresponding terminal.

Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.

Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.

Abstract: A masking and etching technique during the formation of a memory cell capacitor which simultaneously separates storage poly into individual storage poly nodes and etches recesses into the storage poly nodes which increase the surface area of the storage poly nodes and thereby increase the capacitance of a completed memory cell without additional processing steps.

Abstract: A test socket for testing a packaged semiconductor device. The test socket includes a test substrate, at least one support member, and at least one securing member. Terminals of the test substrate are electrically connectable to a testing device. The terminals may by located within recesses that are configured to receive leads. The shapes of each support member and securing member may be complementary to the respective shapes of the bottom and top surfaces of leads extending from the packaged semiconductor device. Upon placement of a packaged semiconductor device on the test substrate, the leads are aligned with and positioned against their corresponding terminals and the support member. The securing elements are then placed against the leads to bias each lead against its corresponding terminal.

Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.

Abstract: The present invention provides a semiconductor device assembly comprising a semiconductor chip, a heat sink having internal and external portions, and a housing that encapsulates the semiconductor chip and the internal portion. The internal portion thermally couples to one surface of the semiconductor chip. The present invention also provides a process of fabricating a semiconductor device assembly. The process includes: providing a semiconductor chip; providing a heat sink having internal and external portions; mechanically attaching a face of the chip to the internal portion; and applying an encapsulating material around the semiconductor chip and the internal portions.

Abstract: A test socket for testing a packaged semiconductor device. The test socket includes a test substrate, at least one support member, and at least one securing member. Terminals of the test substrate are electrically connectable to a testing device. The terminals may by located within recesses that are configured to receive leads. The shapes of each support member and securing member may be complementary to the respective shapes of the bottom and top surfaces of leads extending from the packaged semiconductor device. Upon placement of a packaged semiconductor device on the test substrate, the leads are aligned with and positioned against their corresponding terminals and the support member. The securing elements are then placed against the leads to bias each lead against its corresponding terminal.

Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.

Abstract: A test socket for testing a packaged semiconductor device. The test socket includes a test substrate, at least one support member, and at least one securing member. Terminals of the test substrate are electrically connectable to a testing device. The terminals may by located within recesses that are configured to receive leads. The shapes of each support member and securing member may be complementary to the respective shapes of the bottom and top surfaces of leads extending from the packaged semiconductor device. Upon placement of a packaged semiconductor device on the test substrate, the leads are aligned with and positioned against their corresponding terminals and the support member. The securing elements are then placed against the leads to bias each lead against its corresponding terminal.