Abstract: The present invention relates to the design and implementation of parallel pipelined circuits for the fast Fourier transform (FFT). In this invention, an efficient way of designing FFT circuits using folding transformation and register minimization techniques is proposed. Based on the proposed scheme, novel parallel-pipelined architectures for the computation of complex fast Fourier transform are derived. The proposed architecture takes advantage of under utilized hardware in the serial architecture to derive L-parallel architectures without increasing the hardware complexity by a factor of L. The proposed circuits process L consecutive samples from a single-channel signal in parallel. The operating frequency of the proposed architecture can be decreased which in turn reduces the power consumption. The proposed scheme is general and suitable for applications such as communications, biomedical monitoring systems, and high speed OFDM systems.