Patents by Inventor Manohar R. Castelino

Manohar R. Castelino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160308903
    Abstract: Systems, apparatuses and methods may provide for detecting an attempt by an operating system (OS) to access a non-OS managed resource and injecting, in response to the attempt, an access event into a platform security component via a guest kernel associated with the OS. Additionally, a response to the attempt may be made based on a policy response from the platform security component. In one example, the attempt is detected with respect to one or more extended page table (EPT) permissions set by a security virtual machine monitor (SVMM). Moreover, injecting the access event into the platform security component may include invoking a previously registered policy callback.
    Type: Application
    Filed: December 24, 2015
    Publication date: October 20, 2016
    Applicant: Intel Corporation
    Inventors: Harshawardhan Vipat, Manohar R. Castelino, Barry E. Huntley, Kuo-Lang Tseng
  • Patent number: 9454676
    Abstract: Technologies for monitoring system API calls include a computing device with hardware virtualization support. The computing device establishes a default memory view and a security memory view to define physical memory maps and permissions. The computing device executes an application in the default memory view and executes a default inline hook in response to a call to an API function. The default inline hook switches to the security memory view using hardware support without causing a virtual machine exit. The security inline hook calls a security callback function to validate the API function call in the security memory view. Hook-skipping attacks may be prevented by padding the default inline hook with no-operation instructions, by designating memory pages of the API function as non-executable in the default memory view, or by designating memory pages of the application as non-executable in the security memory view. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: September 27, 2016
    Assignee: Intel Corporation
    Inventors: Harshawardhan Vipat, Manohar R. Castelino, Ravi L. Sahita, Sergio Rodriguez, Vikas Gupta
  • Patent number: 9449173
    Abstract: Various embodiments are directed enabling anti-malware software to co-exist with protective features of an operating system. An apparatus may include a processor component including an IDT register storing an indication of size of an IDT; a monitoring component to retrieve the indication and compare the indication to a size of a guard IDT in response to modification of the IDT register to determine whether the guard routine is to inspect the IDT and a set of ISRs; and a cache component to overwrite the IDT and set of ISRs with a cached IDT and cached set of ISRs, respectively, based on the determination and prior to the inspection to prevent the guard routine from detecting a modification by an anti-malware routine, the cached IDT and cached set of ISRs generated from the IDT and set of ISRs, respectively, prior to the modification. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: September 20, 2016
    Assignee: INTEL CORPORATION
    Inventors: Ramesh Thomas, Manohar R. Castelino, Kuo-Lang Tseng
  • Patent number: 9436838
    Abstract: Apparatus, systems and methods may provide a browser interface to detect an attempt by web content to manipulate data in a local data store. In addition, the data may be classified into a category if the data is remotely accessible. Additionally, a security policy may be applied to the data based on the category. In one example, a separator may separate the data from other data based on the category, the data may be encrypted/decrypted based on the category, and/or context information and user input may be determined to apply the security policy further based on the context information and the user input.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: September 6, 2016
    Assignee: Intel Corporation
    Inventors: Hong C. Li, Mark D. Boucher, Conor P. Cahill, Manohar R. Castelino, Steve Orrin, Vinay Phegade, John E. Simpson, Jr.
  • Publication number: 20160170902
    Abstract: Methods and apparatus relating to low overhead paged memory runtime protection are described. In an embodiment, permission information for guest physical mapping are received prior to utilization of paged memory by an Operating System (OS) based on the guest physical mapping. The permission information is provided through an Extended Page Table (EPT). Other embodiments are also described.
    Type: Application
    Filed: February 23, 2016
    Publication date: June 16, 2016
    Applicant: Intel Corporation
    Inventors: Ravi L. Sahita, Xiaoning Li, Manohar R. Castelino
  • Patent number: 9323564
    Abstract: Systems, methods, and computer program products that provide for the use of a type 2 VMM to de-link or isolate underlying processor hardware from an operating system. This may allow the launching of a task that requires direct access to processor hardware, where such access requires the absence of an operating system. Such a task may take the form of a type 1 VMM, such as an information security or integrity VMM, e.g., an anti-malware VMM.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: April 26, 2016
    Assignee: Intel Corporation
    Inventors: Manohar R. Castelino, Vedvyas Shanbhogue, Sergio Rodriguez
  • Publication number: 20160085967
    Abstract: Various embodiments are directed enabling anti-malware software to co-exist with protective features of an operating system. An apparatus may include a processor component including an IDT register storing an indication of size of an IDT; a monitoring component to retrieve the indication and compare the indication to a size of a guard IDT in response to modification of the IDT register to determine whether the guard routine is to inspect the IDT and a set of ISRs; and a cache component to overwrite the IDT and set of ISRs with a cached IDT and cached set of ISRs, respectively, based on the determination and prior to the inspection to prevent the guard routine from detecting a modification by an anti-malware routine, the cached IDT and cached set of ISRs generated from the IDT and set of ISRs, respectively, prior to the modification. Other embodiments are described and claimed.
    Type: Application
    Filed: September 23, 2014
    Publication date: March 24, 2016
    Inventors: Ramesh Thomas, Manohar R. Castelino, Kuo-Lang Tseng
  • Patent number: 9268707
    Abstract: Methods and apparatus relating to low overhead paged memory runtime protection are described. In an embodiment, permission information for guest physical mapping are received prior to utilization of paged memory by an Operating System (OS) based on the guest physical mapping. The permission information is provided through an Extended Page Table (EPT). Other embodiments are also described.
    Type: Grant
    Filed: December 29, 2012
    Date of Patent: February 23, 2016
    Assignee: Intel Corporation
    Inventors: Ravi L. Sahita, Xiaoning Li, Manohar R. Castelino
  • Publication number: 20150379263
    Abstract: Technologies for monitoring system API calls include a computing device with hardware virtualization support. The computing device establishes a default memory view and a security memory view to define physical memory maps and permissions. The computing device executes an application in the default memory view and executes a default inline hook in response to a call to an API function. The default inline hook switches to the security memory view using hardware support without causing a virtual machine exit. The security inline hook calls a security callback function to validate the API function call in the security memory view. Hook-skipping attacks may be prevented by padding the default inline hook with no-operation instructions, by designating memory pages of the API function as non-executable in the default memory view, or by designating memory pages of the application as non-executable in the security memory view. Other embodiments are described and claimed.
    Type: Application
    Filed: June 27, 2014
    Publication date: December 31, 2015
    Inventors: Harshawardhan Vipat, Manohar R. Castelino, Ravi L. Sahita, Sergio Rodriguez, Vikas Gupta
  • Publication number: 20140223429
    Abstract: Systems, methods, and computer program products that provide for the use of a type 2 VMM to de-link or isolate underlying processor hardware from an operating system. This may allow the launching of a task that requires direct access to processor hardware, where such access requires the absence of an operating system. Such a task may take the form of a type 1 VMM, such as an information security or integrity VMM, e.g., an anti-malware VMM.
    Type: Application
    Filed: December 28, 2011
    Publication date: August 7, 2014
    Inventors: Manohar R. Castelino, Vedvyas Shanbhogue, Sergio Rodriguez
  • Publication number: 20140189194
    Abstract: Methods and apparatus relating to low overhead paged memory runtime protection are described. In an embodiment, permission information for guest physical mapping are received prior to utilization of paged memory by an Operating System (OS) based on the guest physical mapping. The permission information is provided through an Extended Page Table (EPT). Other embodiments are also described.
    Type: Application
    Filed: December 29, 2012
    Publication date: July 3, 2014
    Inventors: RAVI L. SAHITA, XIAONING LI, MANOHAR R. CASTELINO
  • Publication number: 20140181888
    Abstract: Apparatus, systems and methods may provide a browser interface to detect an attempt by web content to manipulate data in a local data store. In addition, the data may be classified into a category if the data is remotely accessible. Additionally, a security policy may be applied to the data based on the category. In one example, a separator may separate the data from other data based on the category, the data may be encrypted/decrypted based on the category, and/or context information and user input may be determined to apply the security policy further based on the context information and the user input.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Inventors: Hong C. Li, Mark D. Boucher, Conor P. Cahill, Manohar R. Castelino, Steve Orrin, Vinay Phegade, John E. Simpson, JR.
  • Patent number: 8719546
    Abstract: Embodiments of techniques and systems for using substitute virtualized-memory page tables are described. In embodiments, a virtual machine monitor (VMM) may determine that a virtualized memory access to be performed by an instruction executing on a guest software virtual machine is not allowed in accordance with a current virtualized-memory page table (VMPT). The VMM may select a substitute VMPT that permits the virtualized memory access, In scenarios where a data access length for the instruction is known, the substitute VMPT may include full execute, read, and write permissions for the entire guest software address space. In scenarios where a data access length for the instruction is not known, the substitute VMPT may include less than full execute, read, and write permissions for the entire guest software address space, and may be modified to allow the requested virtualized memory access. Other embodiments may be described and claimed.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: May 6, 2014
    Assignee: Intel Corporation
    Inventors: Baohong Liu, Manohar R. Castelino, Kuo-Lang Tseng, Ritu Sood, Madhukar Tallam
  • Patent number: 8578080
    Abstract: Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still protecting critical regions of the memory from attacks of malwares. Other embodiments may be disclosed and claimed.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: November 5, 2013
    Assignee: Intel Corporation
    Inventors: Ravi L. Sahita, Xiaoning Li, Manohar R. Castelino
  • Publication number: 20130191611
    Abstract: Embodiments of techniques and systems for using substitute virtualized-memory page tables are described. In embodiments, a virtual machine monitor (VMM) may determine that a virtualized memory access to be performed by an instruction executing on a guest software virtual machine is not allowed in accordance with a current virtualized-memory page table (VMPT). The VMM may select a substitute VMPT that permits the virtualized memory access, In scenarios where a data access length for the instruction is known, the substitute VMPT may include full execute, read, and write permissions for the entire guest software address space. In scenarios where a data access length for the instruction is not known, the substitute VMPT may include less than full execute, read, and write permissions for the entire guest software address space, and may be modified to allow the requested virtualized memory access. Other embodiments may be described and claimed.
    Type: Application
    Filed: January 4, 2013
    Publication date: July 25, 2013
    Inventors: Baohong Liu, Manohar R. Castelino, Kuo-Lang Tseng, Ritu Sood, Madhukar Tallam
  • Patent number: 8479295
    Abstract: Generally, this disclosure describes systems and methods for transparently instrumenting a computer process. The systems and methods are configured to allow instrumenting executable code while permitting legacy memory scanning tools to monitor corresponding uninstrumented executable code stored in memory.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: July 2, 2013
    Assignee: Intel Corporation
    Inventors: Ravi L. Sahita, David M. Durham, Prashant Dewan, Manohar R. Castelino
  • Publication number: 20130007325
    Abstract: Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still protecting critical regions of the memory from attacks of malwares. Other embodiments may be disclosed and claimed.
    Type: Application
    Filed: July 1, 2011
    Publication date: January 3, 2013
    Inventors: Ravi L. Sahita, Xiaoning Li, Manohar R. Castelino
  • Publication number: 20120255015
    Abstract: Generally, this disclosure describes systems and methods for transparently instrumenting a computer process. The systems and methods are configured to allow instrumenting executable code while permitting legacy memory scanning tools to monitor corresponding uninstrumented executable code stored in memory.
    Type: Application
    Filed: March 30, 2011
    Publication date: October 4, 2012
    Inventors: Ravi L. Sahita, David M. Durham, Prashant Dewan, Manohar R. Castelino
  • Patent number: 7349346
    Abstract: A method and apparatus to model routing in a network are described wherein a data test route table (DTRT) is created from a route table, a stream of packets to test the DTRT is generated, and the DTRT is tested using the stream of packets. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventor: Manohar R. Castelino
  • Publication number: 20040085911
    Abstract: A method and apparatus to model routing in a network are described.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 6, 2004
    Inventor: Manohar R. Castelino