Patents by Inventor Manoj Balakrishnan

Manoj Balakrishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230025949
    Abstract: A semiconductor device is provided that includes a lead frame, a die attached to the lead frame using a first solder, a clip attached to the die using a second solder, and a copper slug attached to the clip. First gull wing leads are attached to the leadframe for a drain connection of the semiconductor device. Second gull wing leads are attached to the clip for a gate connection and for a source connection of the semiconductor device.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 26, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Matthew Lloyd Anthony, Ricardo Lagmay Yandoc, Manoj Balakrishnan, Adam Richard Brown
  • Publication number: 20230005846
    Abstract: A semiconductor device is provided, including a leadframe, a die attached to the leadframe using a first solder, a source clip and a gate clip attached to the die using a second solder, and a drain clip attached to the leadframe. The semiconductor device is inverted, so that the source clip and the gate clip are positioned on the bottom side of the semiconductor device, and the leadframe is positioned on the top side of the semiconductor device so that the leadframe is a top exposed drain clip. The source clip and/or the drain clip comprise a half cut locking feature. The half cut locking feature can be formed as a wing and located at the sides of the source clip and the gate clip.
    Type: Application
    Filed: September 13, 2022
    Publication date: January 5, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo Yandoc, Adam Brown, Norman Stapelberg, Manoj Balakrishnan
  • Patent number: 11538795
    Abstract: This disclosure relates to a discrete cascode semiconductor device and associated method of manufacture, the device includes: a high voltage depletion mode device die having gate, source and drain terminals arranged on a first major surface thereof; a low voltage enhancement mode device die having a gate and a source terminal formed on a first major surface thereof, and a drain terminal formed on a second major surface opposite the first major surface. The drain terminal of the high voltage device die is mounted on a drain connection; the source terminal of the low voltage device die and the gate terminal of the high voltage device are mounted on a common source connection; and the drain terminal of the low voltage device die is mounted on the source terminal of the high voltage device.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: December 27, 2022
    Assignee: Nexperia B.V.
    Inventors: Ricardo Lagmay Yandoc, Manoj Balakrishnan
  • Publication number: 20220139724
    Abstract: A semiconductor device including a clip, and the clip includes a clip slot, and a slug and the slug includes a groove. The clip and the slug are attached by the ultrasonic welding. The groove and the clip slot are at least partially overlapping to form a gas pathway.
    Type: Application
    Filed: November 4, 2021
    Publication date: May 5, 2022
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo Yandoc, Anthony Matthew, Manoj Balakrishnan, Adam Brown
  • Publication number: 20200365565
    Abstract: This disclosure relates to a discrete cascode semiconductor device and associated method of manufacture, the device includes: a high voltage depletion mode device die having gate, source and drain terminals arranged on a first major surface thereof; a low voltage enhancement mode device die having a gate and a source terminal formed on a first major surface thereof, and a drain terminal formed on a second major surface opposite the first major surface. The drain terminal of the high voltage device die is mounted on a drain connection; the source terminal of the low voltage device die and the gate terminal of the high voltage device are mounted on a common source connection; and the drain terminal of the low voltage device die is mounted on the source terminal of the high voltage device.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 19, 2020
    Applicant: NEXPERIA B.V.
    Inventors: Ricardo Lagmay Yandoc, Manoj Balakrishnan