Abstract: A method of producing power semiconductor devices from a silicon-on-insulator (SOI) wafer is described. The SOI wafer includes a silicon device layer, a bulk silicon wafer, and a buried oxide layer separating the silicon device layer from the bulk silicon wafer. The method includes: forming a hard mask on the silicon device layer, wherein the hard mask covers one or more first regions of the silicon device layer and exposes one or more second regions of the silicon device layer; and before forming any field oxide structures and before implanting any device regions, selectively growing epitaxial silicon on the one or more second regions of the silicon device layer exposed by the hard mask such that the thickness of the one or more second regions is increased relative to the one or more first regions. Various devices produced according to the method are also described.

Abstract: A semiconductor device includes a silicon-on-insulator (SOI) substrate and transistor cells electrically coupled in parallel to form a power transistor. Each transistor cell includes a source region in a silicon layer of the SOI substrate, a body region in the silicon layer and adjoining the source region, a gate structure configured to control a channel within the body region, a drain region in the silicon layer, and a drift region laterally separating the body region from the drain region. Each gate structure includes a gate electrode separated from the silicon layer by a gate dielectric having a thickness in a range of 20 nm to 60 nm. An effective length of the channel of each transistor cell is in a range of 50 nm to 500 nm. The power transistor has a maximum rated voltage in a range of 5V to 60V. Corresponding methods of producing the semiconductor device are also described.

Abstract: Devices and methods for providing a power transistor structure with a shallow source region include implanting a dopant of a first dopant polarity into a drift region on a source side of a gate structure to form a body region, the body region being self-aligned to, and extending under, the gate structure, and producing a shallow body region wherein the source side hybrid contact mitigates punch through of the shallow self-aligned body region and suppresses triggering of a parasitic bipolar. A retrograde body well, of the first dopant polarity, may be disposed beneath, and noncontiguous with, the shallow self-aligned body region, wherein the retrograde body well improves the electric field profile of the shallow self-aligned body region. A variety of power transistor structures are produced from such devices and methods.

Abstract: A method of fabricating a laterally diffused metal oxide semiconductor transistor including providing a substrate, forming a first well of a first doping polarity type in the substrate, forming a gate on a portion of the first well, the gate including an oxide layer and an at least partially conductive layer on the oxide layer, and forming a mask on at least a portion of the gate and at least a portion of the first well, wherein the mask has a sloping edge. The method further includes forming a second well of a second doping polarity type at least partially in the first well by implanting ions in the first well, the second well extending under a portion of the gate, the second doping polarity type being of opposite type to the first doping polarity type. The method includes forming a first one of a source and drain of the first doping polarity type in or on the second well, thereby defining a channel of the transistor under the gate.

Abstract: Devices and methods for providing a power transistor structure with a shallow source region include implanting a dopant of a first dopant polarity into a drift region on a source side of a gate structure to form a body region, the body region being self-aligned to, and extending under, the gate structure, and producing a shallow body region wherein the source side hybrid contact mitigates punch through of the shallow self-aligned body region and suppresses triggering of a parasitic bipolar. A retrograde body well, of the first dopant polarity, may be disposed beneath, and noncontiguous with, the shallow self-aligned body region, wherein the retrograde body well improves the electric field profile of the shallow self-aligned body region. A variety of power transistor structures are produced from such devices and methods.

Abstract: Devices and methods for providing a power transistor structure with a shallow source region include implanting a dopant of a first dopant polarity into a drift region on a source side of a gate structure to form a body region, the body region being self-aligned to, and extending under, the gate structure, and producing a shallow body region wherein the source side hybrid contact mitigates punch through of the shallow self-aligned body region and suppresses triggering of a parasitic bipolar. A retrograde body well, of the first dopant polarity, may be disposed beneath, and noncontiguous with, the shallow self-aligned body region, wherein the retrograde body well improves the electric field profile of the shallow self-aligned body region. A variety of power transistor structures are produced from such devices and methods.

Abstract: Methods of fabricating a field-effect transistor, where the methods include providing a substrate, forming a first well of a first doping polarity type in the substrate, and forming a gate on a portion of the first well, the gate comprising an oxide layer and an at least partially conductive layer on the oxide layer. A second well of a second doping polarity type is formed by implanting ions in the first well, the second well extending under a portion of the gate. A first one of a source and drain of the first doping polarity type in or on the second well is formed, thereby defining a channel of the transistor under the gate. A second one of the source and drain of the first doping polarity type in or on the first well is formed. The second well may be formed by means of a two-step implant.

Abstract: A method of fabricating a laterally diffused metal oxide semiconductor transistor including providing a substrate, forming a first well of a first doping polarity type in the substrate, forming a gate on a portion of the first well, the gate including an oxide layer and an at least partially conductive layer on the oxide layer, and forming a mask on at least a portion of the gate and at least a portion of the first well, wherein the mask has a sloping edge. The method further includes forming a second well of a second doping polarity type at least partially in the first well by implanting ions in the first well, the second well extending under a portion of the gate, the second doping polarity type being of opposite type to the first doping polarity type. The method includes forming a first one of a source and drain of the first doping polarity type in or on the second well, thereby defining a channel of the transistor under the gate.

Abstract: Methods of fabricating a field-effect transistor, where the methods include providing a substrate, forming a first well of a first doping polarity type in the substrate, and forming a gate on a portion of the first well, the gate comprising an oxide layer and an at least partially conductive layer on the oxide layer. A second well of a second doping polarity type is formed by implanting ions in the first well, the second well extending under a portion of the gate. A first one of a source and drain of the first doping polarity type in or on the second well is formed, thereby defining a channel of the transistor under the gate. A second one of the source and drain of the first doping polarity type in or on the first well is formed. The second well may be formed by means of a two-step implant.