Abstract: Integrated circuits having electrical interconnection in a multi-chip module or package is provided. Connections involving topological cross overs are achieved in the absence of multi-layers of metalization or vias. A plurality of metal traces in a single metalization layer are provided. Wire bonding issued to connect pads from two or more chips to a common metalization trace. Because the wire bonds can be vertically spaced from substrate traces, crossover connections can be achieved without an unwanted contact between traces and pads. A similar scheme can be used to provide connection to substrate pads.