Abstract: A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

Abstract: A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

Abstract: A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

Abstract: A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

Abstract: A data processing system is comprised of: a system bus having a main memory coupled thereto; multiple high level cache memories, each of which has a first port coupled to said system bus and a second port coupled to a respective processor bus; and each processor bus being coupled through respective low level cache memories to respective digital computers. In the high level cache memories, data words are stored with respective tag bits which identify each data word as being stored in one of only four states which are shared, modified, invalid, or exclusive. In the low level cache memories, data words are stored with respective tag bits which identify each data word as being stored in only one of three states which are shared, modified or invalid.

Abstract: A method and system for arranging and operating a multiprocessor computer server system having "split-transaction bus" architecture, including bus modules operating with an address phase and a cycle phase. The bus modules are arranged for access by a prescribed resource stage to facilitate "RETRY" operations. The method includes providing a Cache Tag and Address Compare, arranging the system so that a first bus module stores the address for the Resource stage in the Cycle Tag; and comparing subsequent address bus cycles to the contents of the Cache Tag so that, given a "match", a "RETRY" direction is responsively sent to any other bus module that requests access. The system provides components supporting the above method steps.

Abstract: A multi-clock pulse synchronizer circuit with and IN-section receiving and storing prescribed in-pulses and input clock signals and responsively outputting intermediate pulses; and an OUT-section for receiving and storing the intermediate pulses, synchronous with certain output clock signals and processing them to generate certain output-signals, for better avoiding metastability.

Abstract: A method of arranging and operating a cache in a multi-processor computer system with N local processors, where a requesting device can request a cycle to be issued, where the method involves "posting" the "cycles", while also storing information for completing a cycle in a Queue and causing the requesting device to be issued "termination" immediately, rather than waiting for the cycle to reach its destination.

Abstract: In a multiprocessor computer system where a number of "agents" can compete for access to a "resource", a method of ameliorating "Livelock" and preventing any such agent from being unduly frustrated from such access, this method comprising: arranging the system to include an arbitrating unit and a common system bus connecting a number of processors, plus an Avoidance unit included in each processor and including a Random-Number generator and automatic "Random Backoff" that causes an agent that fails to secure access to wait for one or more given random time periods T.sup.B before reattempting such access, with each said time period T.sup.B being provided by the random number generator so as to likely differentiate from competing agents.

Abstract: In a multiprocessor computer system where a number of "agents" can compete for access to a "resource", a method of ameliorating "Livelock" and preventing any such agent from being unduly frustrated from such access, this method comprising: arranging the system to include an arbitrating unit and a common system bus connecting a number of processors, plus an Avoidance unit included in each processor and including a Random-Number generator and automatic "Random Backoff" that causes an agent that fails to secure access to wait for one or more given random time periods T.sub.B before reattempting such access, with each said time period T.sub.B being provided by the random number generator so as to likely differentiate from competing agents.

Abstract: A method of arranging and operating a multiprocessor computer server system having "split-transaction bus" architecture, including bus modules operating with an address phase and a cycle phase, and arranged for access by a prescribed resource stage, to facilitate "RETRY", this method including; providing a Cache Tag and Address Compare,arranging the system so that a first bus module stores the address for the Resource stage in the Cycle Tag; andcomparing subsequent address bus cycles to the contents of the Cache Tag so that, givena "match", a "RETRY" direction is responsively sent to any other bus module that requests access.

Abstract: Described are techniques to stabilize storage devices receiving signals from plural asynchronous docks, especially to avoid "metastability", in particular, a multi-dock pulse synchronizer circuit with an IN-section for receiving and storing prescribed impulses and input cock signals, and for responsively outputting intermediate signals: and an OUT-section for receiving and storing the intermediate pulses, synchronous with certain output clock signals and processing them to generate certain output-signals which avoid metastability.