Abstract: A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.

Abstract: A Signal Processing Engine (SPE) includes circuitry for generating a selectable forward tap and a selectable reverse tap from a forward delay chain and a reverse delay chain, respectively. An add/subtract unit arithmetically combines the selectable forward tap and the selectable reverse tap to generate an intermediate output. A multiplier combines the intermediate output and a coefficient output from a circular coefficient buffer to generate a multiply result. Another adder/subtractor combines the multiply result with a second term including a processed input or an accumulator feedback by bypassing, adding, or subtracting the second term with the multiply result to generate an accumulator output. The accumulator output may be delayed a programmable number of clock cycles to generate a processed output. In some embodiments, the SPE is coupled to programmable logic blocks forming a programmable logic array through a programmable SPE routing block.

Abstract: A CORDIC engine includes an N-stage CORDIC processor for performing N micro-iterations of a CORDIC algorithm and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input. A counter counts a number of M macro-iterations for the CORDIC algorithm and indicates a start of the cycle iterations. A multiplexer selects an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times. The CORDIC algorithm is complete after N*M clock cycles by generating N micro-iterations for each of the M macro-iterations. In some embodiments, the CORDIC engine is coupled to programmable logic blocks as part of a programmable logic array.

Abstract: A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.

Abstract: A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.

Abstract: A memory is disclosed that can be utilized with a field programmable gate array. In some embodiments, the memory can include a memory array comprising a plurality of memory banks, each memory bank including at least one memory block, each of the at least one memory block including an array of memory cells; an address decoder coupled to each of the at least one memory block, the address decoder including a comparator coupled to receive an input address and a block address and provide a compare bit that indicates when a portion of the input address matches the block address, and an OR gate coupled to receive the compare bit and a wildcard bit, the OR gate providing an enable to the memory block when either the compare bit or the wildcard bit is asserted; and a logic unit that receives a mode value and the input address and provides the wildcard bit to each of the address decoders. Data can be simultaneously written into the memory array in patterns in accordance with the mode value.

Abstract: A Signal Processing Engine (SPE) includes circuitry for generating a selectable forward tap and a selectable reverse tap from a forward delay chain and a reverse delay chain, respectively. An add/subtract unit arithmetically combines the selectable forward tap and the selectable reverse tap to generate an intermediate output. A multiplier combines the intermediate output and a coefficient output from a circular coefficient buffer to generate a multiply result. Another adder/subtractor combines the multiply result with a second term including a processed input or an accumulator feedback by bypassing, adding, or subtracting the second term with the multiply result to generate an accumulator output. The accumulator output may be delayed a programmable number of clock cycles to generate a processed output. In some embodiments, the SPE is coupled to programmable logic blocks forming a programmable logic array through a programmable SPE routing block.

Abstract: A CORDIC engine includes an N-stage CORDIC processor for performing N micro-iterations of a CORDIC algorithm and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input. A counter counts a number of M macro-iterations for the CORDIC algorithm and indicates a start of the cycle iterations. A multiplexer selects an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times. The CORDIC algorithm is complete after N*M clock cycles by generating N micro-iterations for each of the M macro-iterations. In some embodiments, the CORDIC engine is coupled to programmable logic blocks as part of a programmable logic array.

Abstract: A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.

Abstract: A memory is disclosed that can be utilized with a field programmable gate array. In some embodiments, the memory can include a memory array comprising a plurality of memory banks, each memory bank including at least one memory block, each of the at least one memory block including an array of memory cells; an address decoder coupled to each of the at least one memory block, the address decoder including a comparator coupled to receive an input address and a block address and provide a compare bit that indicates when a portion of the input address matches the block address, and an OR gate coupled to receive the compare bit and a wildcard bit, the OR gate providing an enable to the memory block when either the compare bit or the wildcard bit is asserted; and a logic unit that receives a mode value and the input address and provides the wildcard bit to each of the address decoders. Data can be simultaneously written into the memory array in patterns in accordance with the mode value.

Abstract: A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.

Abstract: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function.

Abstract: A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.

Abstract: A programmable logic array for use in a field programmable application specific integrated circuit (ASIC) implementation is provided. The programmable logic array includes programmable logic blocks, and programmable logic interfaces. The programmable logic interfaces couple the programmable logic blocks to external interfaces of the field programmable ASIC, and enable the programmable logic array to be inserted into the field programmable ASIC as a hard macro block.

Abstract: A programmable logic array for use in a field programmable application specific integrated circuit (ASIC) implementation is provided. The programmable logic array includes programmable logic blocks, and programmable logic interfaces. The programmable logic interfaces couple the programmable logic blocks to external interfaces of the field programmable ASIC, and enable the programmable logic array to be inserted into the field programmable ASIC as a hard macro block.

Abstract: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In some embodiments, the configurable logic function comprises a plurality of look-up tables coupled to a multiplexer with configurable bits that is capable to perform a four 4-input look-up table, one 6-input look-up tables or a 4-to-1 multiplexer. In the first function that operates as the four 4-input look-up table, the dedicated logic cell has four look-up tables for receiving four inputs respectively.

Abstract: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function.

Abstract: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function.

Abstract: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic function, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function.

Abstract: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function.