Abstract: Higher grade VG bitumens are prepared particularly by blending of 0.1 to 20 wt % specific Sulfur-Based Polymeric Additives (SBPA) having MW 1,000 to 10,000 Dalton. The prepared higher grade VG bitumens have Kinematic Viscosity of from 200 cSt to 1000 cSt measured at 135° C. from Base bitumen (VG10) at a temperature from 100° C. to 140° C. and stirring in the range of 800 rpm to 1200 rpm for 30 minutes to 90 minutes for improving the properties of bitumens and to make higher grades of Bitumens (VG20, VG30, VG40) for industrial applications.

Abstract: A method and apparatus for polishing a substrate is disclosed herein. More specifically, the apparatus relates to an integrated CMP system for polishing substrates. The CMP system has a polishing station configured to polish substrates. A spin rinse dry (SRD) station configured to clean and dry the substrates. A metrology station configured to measure parameters of the substrates. A robot configured to move the substrate in to and out of the SRD station. And an effector rinse and dry (EERD) station configured to clean and dry an end effector of the robot.

Abstract: Fused bicyclic compounds are inhibitors of GPR91. The compounds, their stereoisomers, tautomers, prodrugs, polymorphs, solvates, pharmaceutically acceptable salts, and pharmaceutical compositions containing them are useful in the treatment, prevention, prophylaxis, management, or adjunct treatment of all medical conditions related to inhibition of GPR91.

Abstract: Fused bicyclic compounds are inhibitors of GPR91. The compounds, their stereoisomers, tautomers, prodrugs, polymorphs, solvates, pharmaceutically acceptable salts, and pharmaceutical compositions containing them are useful in the treatment, prevention, prophylaxis, management, or adjunct treatment of all medical conditions related to inhibition of GPR91.

Abstract: Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.

Abstract: Methods form devices by patterning a lower layer to form a fin, and forming a sacrificial gate along sidewalls of the fin. Such methods form a mask with cut openings on the sacrificial gate and remove sections of the fin and the sacrificial gate exposed through the cut openings to divide the fin into fin portions and create cut areas between the fin portions. Additionally, these methods remove the mask, epitaxially grow source/drains in the cut areas, replace the sacrificial gate with a gate conductor, and form a gate contact on the gate conductor over a center of the fin portions.

Abstract: A system is provided and includes search, analytics acquisition, CTR, and scoring modules. The search module: receives query requests from one or more user devices for respective queries; and based on the query requests and a CTR-based scoring model, conducts searches to provide search results for the queries. The analytics acquisition module acquires analytics data corresponding to the queries. The analytics data includes query files for the queries and selection files for the queries for which a selection event occurred. At least some of the selection events occur when a user of the one or more user devices selects a search result item in the search results provided for the queries. The CTR module determines a normalized CTR based on the analytics data. The scoring module updates the CTR-based scoring model based on the normalized CTR. The search module conducts a search based on the updated CTR-based scoring model.

Abstract: Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the varying gate structure including a first gate stack in a first region of the substrate structure, and a second gate stack in a second region of the substrate structure; a first field-effect transistor in the first region, the first field-effect transistor including the first gate stack and having a first threshold voltage; and a second field-effect transistor in the second region, the second field-effect transistor including the second gate stack and having a second threshold voltage, where the first threshold voltage is different from the second threshold voltage. The methods include providing the varying gate structure, the providing including: sizing layer(s) of the varying gate structure with different thickness(es) in different region(s).

Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.

Abstract: In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.

Abstract: Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the varying gate structure including a first gate stack in a first region of the substrate structure, and a second gate stack in a second region of the substrate structure; a first field-effect transistor in the first region, the first field-effect transistor including the first gate stack and having a first threshold voltage; and a second field-effect transistor in the second region, the second field-effect transistor including the second gate stack and having a second threshold voltage, where the first threshold voltage is different from the second threshold voltage. The methods include providing the varying gate structure, the providing including: sizing layer(s) of the varying gate structure with different thickness(es) in different region(s).

Abstract: In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage.

Abstract: In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.

Abstract: One illustrative method disclosed includes, among other things, forming a fin in a substrate, forming a well implant region in at least the substrate, forming a punch-stop implant region in the fin, performing at least one neutral implantation process with at least one neutral implant material to form a neutral boron-diffusion-blocking implant region in the fin, wherein an upper surface of the neutral boron-diffusion-blocking implant region is positioned closer to an upper surface of the fin than either the punch-stop implant region or the well implant region and, after forming the well implant region, the punch-stop implant region and the neutral boron-diffusion-blocking implant region, forming a gate structure above the fin.