Patents by Inventor Manoj Kumar Dey

Manoj Kumar Dey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7825809
    Abstract: A marking system or identification code for a flexible circuit or cable is disclosed. The system provides individual tracking for flexible circuits or cables assembled in data storage systems. As described, the flexible circuit or cable includes an identification code or marking on a flexible substrate for providing individual tracking for a flexible circuit or cable of a data storage device.
    Type: Grant
    Filed: January 7, 2004
    Date of Patent: November 2, 2010
    Assignee: Seagate Technology LLC
    Inventors: Joon Hwa Lim, Manoj Kumar Dey
  • Patent number: 7173438
    Abstract: A method for determining capacitance includes alternately charging a capacitor to a first voltage and discharging the capacitor to a second voltage, generating an output signal having a frequency that is a function of a time period, and determining the capacitance based on the frequency of the output signal. The time period is selected from at least one of: (a) a time period needed to charge the capacitor from the second voltage to the first voltage and (b) a time period needed to discharge the capacitor from the first voltage to the second voltage.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: February 6, 2007
    Assignee: Seagate Technology LLC
    Inventors: Pooranampillai Samuel Pooranakaran, Vasudevan Seshadri Kumar, Manoj Kumar Dey, Chung See Fook
  • Patent number: 6920624
    Abstract: A method and apparatus for translating a Gerber data file into a data format usable by vision software through a process whereby a first Gerber data element is selected and examined to determine if the shape represented by that element intersects with any other shapes. Each shape intersecting the selected element is merged into a single data object with the selected element. This process is repeated for each element describing the printed circuit board layout. The consequence of this procedure is that complex geometries that had been represented as the intersection of many simple geometries are represented as individual data objects.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: July 19, 2005
    Assignee: Seagate Technology, LLC
    Inventors: Srinivas Garrepally, Sim ChingTong, Channasumudram Krishnamurthy Sowmithri, Manoj Kumar Dey
  • Patent number: 6807507
    Abstract: An apparatus and associated method for testing an integrated circuit for electrical over stress includes a spike source configured to couple to an input of the integrated circuit, and responsively provide a signal spike to the input, and a current sensor configured to couple to a power supply. The power supply is coupled to the integrated circuit to provide power to the integrated circuit. The current sensor provides a sensor output related to the current supply to the integrated circuit from the power supply. The apparatus also includes test circuitry coupled to the sensor output configured to provide a failure output in response to a characteristic increase in power supply current sensed by the current sensor in response to an applied signal spike.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: October 19, 2004
    Inventors: Vasudevan Seshadhri Kumar, Manoj Kumar Dey, Pooranampillai Samuel Pooranakaran, KyawSwa Maung
  • Publication number: 20030135829
    Abstract: A method and apparatus for translating a Gerber data file into a data format usable by vision software through a process whereby a first Gerber data element is selected and examined to determine if the shape represented by that element intersects with any other shapes. Each shape intersecting the selected element is merged into a single data object with the selected element. This process is repeated for each element describing the printed circuit board layout. The consequence of this procedure is that complex geometries that had been represented as the intersection of many simple geometries are represented as individual data objects.
    Type: Application
    Filed: June 28, 2002
    Publication date: July 17, 2003
    Inventors: Srinivas Garrepally, Sim ChingTong, Channasumudram Krishnamurthy Sowmithri, Manoj Kumar Dey
  • Publication number: 20030101016
    Abstract: An apparatus and associated method for testing an integrated circuit for electrical over stress includes a spike source configured to couple to an input of the integrated circuit, and responsively provide a signal spike to the input, and a current sensor configured to couple to a power supply. The power supply is coupled to the integrated circuit to provide power to the integrated circuit. The current sensor provides a sensor output related to the current supply to the integrated circuit from the power supply. The apparatus also includes test circuitry coupled to the sensor output configured to provide a failure output in response to a characteristic increase in power supply current sensed by the current sensor in response to an applied signal spike.
    Type: Application
    Filed: June 27, 2002
    Publication date: May 29, 2003
    Inventors: Vasudevan Seshadhri Kumar, Manoj Kumar Dey, Pooranampillai Samuel Pooranakaran, KyawSwa Maung